LIDE: a simulation environment for shared virtual memory systems. - Salvador Petit; José A. Gil 001; Julio Sahuquillo; Ana Pont (SIGARCH Comput. Archit. News, 2000)

About the sensitivity of the HLRC-DU protocol on diff and page sizes. - Salvador Petit; Julio Sahuquillo; Ana Pont (ISPASS, 2001)

Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems. - Salvador Petit; Julio Sahuquillo; Ana Pont (PDP, 2002)

Characterizing the Dynamic Behavior of Workload Execution in SVM systems. - Salvador Petit; Julio Sahuquillo; Ana Pont; David R. Kaeli (SBAC-PAD, 2004)

Exploiting temporal locality in drowsy cache policies. - Salvador Petit; Julio Sahuquillo; Jose M. Such; David R. Kaeli (Conf. Computing Frontiers, 2005)

A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol. - Salvador Petit; Julio Sahuquillo; Ana Pont (PDP, 2005)

Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. - Julio Sahuquillo; Salvador Petit; Ana Pont; Veljko M. Milutinovic (J. Syst. Archit., 2005)

Applying the zeros switch-off technique to reduce static energy in data caches. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001 (SBAC-PAD, 2006)

An execution-driven simulation tool for teaching cache memories in introductory computer organization courses. - Salvador Petit; Noel Tomás; Julio Sahuquillo; Ana Pont (WCAE, 2006)

RACFP: a training tool to work with floating-point representation, algorithms, and circuits in undergraduate courses. - Rafael Ubal; Juan-Carlos Cano; Salvador Petit; Julio Sahuquillo (IEEE Trans. Educ., 2006)

Addressing a workload characterization study to the design of consistency protocols. - Salvador Petit; Julio Sahuquillo; Ana Pont; David R. Kaeli (J. Supercomput., 2006)

VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (PACT, 2007)

Leakage Current Reduction in Data Caches on Embedded Systems. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Houcine Hassan; Pedro López 001 (IPC, 2007)

Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001 (SBAC-PAD, 2007)

Spim-Cache: A Pedagogical Tool for Teaching Cache Memories Through Code-Based Exercises. - Julio Sahuquillo; Noel Tomás; Salvador Petit; Ana Pont (IEEE Trans. Educ., 2007)

Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. - Noel Tomás; Julio Sahuquillo; Salvador Petit; Pedro López 001 (Euro-Par, 2008)

A simple power-aware scheduling for multicore systems when running real-time applications. - Diana Bautista; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (IPDPS, 2008)

The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (IPDPS, 2008)

An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. - Salvador Petit; Rafael Ubal; Julio Sahuquillo; Pedro López 001; José Duato (DSD, 2009)

Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001 (Euro-Par, 2009)

A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. - Salvador Petit; Rafael Ubal; Julio Sahuquillo; Pedro López 001 (ICCD, 2009)

Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. - Diana Bautista; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (ICS, 2009)

An hybrid eDRAM/SRAM macrocell to implement first-level data caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Vicente Lorente; Ramon Canal; Pedro López 001; José Duato (MICRO, 2009)

Power Reduction In Advanced Embedded IPC Processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Houcine Hassan; Pedro López 001 (Intell. Autom. Soft Comput., 2009)

A Complexity-Effective Out-of-Order Retirement Microarchitecture. - Salvador Petit Marti; Julio Sahuquillo Borrás; Pedro Juan López Rodríguez; Rafael Ubal Tena; José Duato Marín (IEEE Trans. Computers, 2009)

Exploiting subtrace-level parallelism in clustered processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (PACT, 2010)

A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. - Monica Serrano; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (HPCC, 2010)

Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems. - José Luis March; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (ICA3PP (2), 2010)

Out-of-order retirement of instructions in sequentially consistent multiprocessors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; David R. Kaeli (ICCD, 2010)

Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. - Diana Bautista Rayo; Julio Sahuquillo Borrás; Houcine Hassan Mohamed; Salvador Petit; José Duato (PDP, 2010)

Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption. - Diana Bautista; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (SAC, 2010)

Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (PACT, 2011)

A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems. - José Luis March; Julio Sahuquillo; Salvador Petit; Houcine Hassan; José Duato (Euro-Par (1), 2011)

A Cluster Computer Performance Predictor for Memory Scheduling. - Monica Serrano; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (ICA3PP (2), 2011)

MRU-Tour-based Replacement Algorithms for Last-Level Caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (SBAC-PAD, 2011)

A New Energy-Aware Dynamic Task Set Partitioning Algorithm for Soft and Hard Embedded Real-Time Systems. - José Luis March; Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Duato (Comput. J., 2011)

OMHI 2012: First International Workshop on On-chip Memory Hierarchies and Interconnects: Organization, Management and Implementation. - Julio Sahuquillo; María Engracia Gómez; Salvador Petit (Euro-Par Workshops, 2012)

Analyzing the optimal ratio of SRAM banks in hybrid caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (ICCD, 2012)

Page-Based Memory Allocation Policies of Local and Remote Memory in Cluster Computers. - Monica Serrano; Salvador Petit; Julio Sahuquillo; Rafael Ubal; Houcine Hassan; José Duato (ICPADS, 2012)

Understanding Cache Hierarchy Contention in CMPs to Improve Job Scheduling. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (IPDPS, 2012)

Efficiently Handling Memory Accesses to Improve QoS in Multicore Systems under Real-Time Constraints. - José Luis March; Salvador Petit; Julio Sahuquillo; Houcine Hassan; José Duato (SBAC-PAD, 2012)

Combining recency of information with selective random and a victim cache in last-level caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (ACM Trans. Archit. Code Optim., 2012)

Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. - Alejandro Valero; Salvador Petit; Julio Sahuquillo; Pedro López 001; José Duato (IEEE Trans. Computers, 2012)

A cost-effective heuristic to schedule local and remote memory in cluster computers. - Monica Serrano; Julio Sahuquillo; Salvador Petit; Houcine Hassan; José Duato (J. Supercomput., 2012)

A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; David R. Kaeli (IEEE Trans. Parallel Distributed Syst., 2012)

Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. - Alejandro Valero; Julio Sahuquillo; Vicente Lorente; Salvador Petit; Pedro López 001; José Duato (IEEE Trans. Very Large Scale Integr. Syst., 2012)

L1-bandwidth aware thread allocation in multicore SMT processors. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (PACT, 2013)

Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. - Vicente Lorente; Alejandro Valero; Julio Sahuquillo; Salvador Petit; Ramon Canal; Pedro López 001; José Duato (DATE, 2013)

Using Huge Pages and Performance Counters to Determine the LLC Architecture. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (ICCS, 2013)

Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; José Duato (ICS, 2013)

Power-aware scheduling with effective task migration for real-time multicore embedded systems. - José Luis March; Julio Sahuquillo; Salvador Petit; Houcine Hassan; José Duato (Concurr. Comput. Pract. Exp., 2013)

Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors. - Rafael Ubal; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (IEEE Trans. Computers, 2013)

Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. - Vicente Lorente; Alejandro Valero; Salvador Petit; Pierfrancesco Foglia; Julio Sahuquillo (HPCC/CSS/ICESS, 2014)

Dynamic WCET Estimation for Real-Time Multicore Embedded Systems Supporting DVFS. - José Luis March; Salvador Petit; Julio Sahuquillo; Houcine Hassan; José Duato (HPCC/CSS/ICESS, 2014)

Addressing bandwidth contention in SMT multicores through scheduling. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (ICS, 2014)

Cache-Hierarchy Contention-Aware Scheduling in CMPs. - Josué Feliu; Salvador Petit; Julio Sahuquillo; José Duato (IEEE Trans. Parallel Distributed Syst., 2014)

Efficient Register Renaming and Recovery for High-Performance Processors. - Salvador Petit; Rafael Ubal; Julio Sahuquillo; Pedro López 001 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Accurately modeling the GPU memory subsystem. - Francisco Candel; Salvador Petit; Julio Sahuquillo; José Duato (HPCS, 2015)

Current challenges in simulations of HPC systems. - Salvador Petit (HPCS, 2015)

Addressing Fairness in SMT Multicores with a Progress-Aware Scheduler. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (IPDPS, 2015)

A Research-Oriented Course on Advanced Multicore Architecture. - Julio Sahuquillo; Salvador Petit; Vicent Selfa; María Engracia Gómez (IPDPS Workshops, 2015)

A reuse-based refresh policy for energy-aware eDRAM caches. - Alejandro Valero; Salvador Petit; Julio Sahuquillo; David R. Kaeli; José Duato (Microprocess. Microsystems, 2015)

Design of Hybrid Second-Level Caches. - Alejandro Valero; Julio Sahuquillo; Salvador Petit; Pedro López 001; José Duato (IEEE Trans. Computers, 2015)

Student Research Poster: A Low Complexity Cache Sharing Mechanism to Address System Fairness. - Vicent Selfa; Julio Sahuquillo; Salvador Petit; María Engracia Gómez (PACT, 2016)

Symbiotic job scheduling on the IBM POWER8. - Josué Feliu; Stijn Eyerman; Julio Sahuquillo; Salvador Petit (HPCA, 2016)

Accurately modeling a photonic NoC in a detailed CMP simulation framework. - José Puche; Sergio Lechago; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (HPCS, 2016)

Impact of Memory-Level Parallelism on the Performance of GPU Coherence Protocols. - Francisco Candel; Salvador Petit; Julio Sahuquillo; José Duato (PDP, 2016)

Enhancing the L1 Data Cache Design to Mitigate HCI. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Comput. Archit. Lett., 2016)

A dynamic execution time estimation model to save energy in heterogeneous multicores running periodic tasks. - Julio Sahuquillo; Houcine Hassan; Salvador Petit; José Luis March; José Duato (Future Gener. Comput. Syst., 2016)

Bandwidth-Aware On-Line Scheduling in SMT Multicores. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (IEEE Trans. Computers, 2016)

Application Clustering Policies to Address System Fairness with Intel's Cache Allocation Technology. - Vicent Selfa; Julio Sahuquillo; Lieven Eeckhout; Salvador Petit; María Engracia Gómez (PACT, 2017)

Modeling a Photonic Network for Exascale Computing. - Jose Duro; Salvador Petit; Julio Sahuquillo; María Engracia Gómez (HPCS, 2017)

Exploiting Data Compression to Mitigate Aging in GPU Register Files. - Francisco Candel; Alejandro Valero; Salvador Petit; Darío Suárez Gracia; Julio Sahuquillo (SBAC-PAD, 2017)

A research-oriented course on Advanced Multicore Architecture: Contents and active learning methodologies. - Salvador Petit; Julio Sahuquillo; María Engracia Gómez; Vicent Selfa (J. Parallel Distributed Comput., 2017)

Perf&Fair: A Progress-Aware Scheduler to Enhance Performance and Fairness in SMT Multicores. - Josué Feliu; Julio Sahuquillo; Salvador Petit; José Duato (IEEE Trans. Computers, 2017)

Improving IBM POWER8 Performance Through Symbiotic Job Scheduling. - Josué Feliu; Stijn Eyerman; Julio Sahuquillo; Salvador Petit; Lieven Eeckhout (IEEE Trans. Parallel Distributed Syst., 2017)

A Hardware Approach to Fairly Balance the Inter-Thread Interference in Shared Caches. - Vicent Selfa; Julio Sahuquillo; Salvador Petit; María Engracia Gómez (IEEE Trans. Parallel Distributed Syst., 2017)

On Microarchitectural Mechanisms for Cache Wearout Reduction. - Alejandro Valero; Negar Miralaei; Salvador Petit; Julio Sahuquillo; Timothy M. Jones 001 (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Improving GPU Cache Hierarchy Performance with a Fetch and Replacement Cache. - Francisco Candel; Salvador Petit; Alejandro Valero; Julio Sahuquillo (Euro-Par, 2018)

Improving System Turnaround Time with Intel CAT by Identifying LLC Critical Applications. - Lucia Pons; Vicent Selfa; Julio Sahuquillo; Salvador Petit; Julio Pons Terol (Euro-Par, 2018)

Workload Characterization for Exascale Computing Networks. - Jose Duro; Salvador Petit; Julio Sahuquillo; María Engracia Gómez (HPCS, 2018)

A Workload Generator for Evaluating SMT Real-Time Systems. - Clara Furió; Josué Feliu; Salvador Petit; Jose Duro; Julio Sahuquillo (HPCS, 2018)

Accurately modeling the on-chip and off-chip GPU memory subsystem. - Francisco Candel; Salvador Petit; Julio Sahuquillo; José Duato (Future Gener. Comput. Syst., 2018)

Designing lab sessions focusing on real processors for computer architecture courses: A practical perspective. - Josué Feliu; Julio Sahuquillo; Salvador Petit (J. Parallel Distributed Comput., 2018)

Modeling and analysis of the performance of exascale photonic networks. - Jose Duro; Jose Antonio Pascual; Salvador Petit; Julio Sahuquillo; María Engracia Gómez (Concurr. Comput. Pract. Exp., 2019)

Efficient Management of Cache Accesses to Boost GPGPU Memory Subsystem Performance. - Francisco Candel; Alejandro Valero; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2019)

An Aging-Aware GPU Register File Design Based on Data Redundancy. - Alejandro Valero; Francisco Candel; Darío Suárez Gracia; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2019)

FOS: a low-power cache organization for multicores. - José Puche; Salvador Petit; Julio Sahuquillo; María Engracia Gómez (J. Supercomput., 2019)

Way Combination for an Adaptive and Scalable Coherence Directory. - J. Rubén Titos Gil; Antonio Flores; Ricardo Fernández-Pascual; Alberto Ros 001; Salvador Petit; Julio Sahuquillo; Manuel E. Acacio (IEEE Trans. Parallel Distributed Syst., 2019)

Impact of the Array Shape and Memory Bandwidth on the Execution Time of CNN Systolic Arrays. - Eduardo Yago; Pau Castelló; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (DSD, 2020)

Understanding Cloud Workloads Performance in a Production like Environment. - Lucia Pons; Josué Feliu; José Puche; Chaoyi Huang; Salvador Petit; Julio Pons; María Engracia Gómez; Julio Sahuquillo (CoRR, 2020)

An efficient cache flat storage organization for multithreaded workloads for low power processors. - José Puche; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (Future Gener. Comput. Syst., 2020)

Thread Isolation to Improve Symbiotic Scheduling on SMT Multicore Processors. - Josué Feliu; Julio Sahuquillo; Salvador Petit; Lieven Eeckhout (IEEE Trans. Parallel Distributed Syst., 2020)

Bandwidth-Aware Dynamic Prefetch Configuration for IBM POWER8. - Carlos Navarro; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (IEEE Trans. Parallel Distributed Syst., 2020)

Phase-Aware Cache Partitioning to Target Both Turnaround Time and System Performance. - Lucia Pons; Julio Sahuquillo; Vicent Selfa; Salvador Petit; Julio Pons (IEEE Trans. Parallel Distributed Syst., 2020)

Segment Switching: A New Switching Strategy for Optical HPC Networks. - Jose Duro; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (IEEE Access, 2021)

Cache-Poll: Containing Pollution in Non-Inclusive Caches Through Cache Partitioning. - Lucia Pons; Julio Sahuquillo; Salvador Petit; Julio Pons (ICPP, 2022)

Fast-track cache: a huge racetrack memory L1 data cache. - Hugo Tárrega; Alejandro Valero; Vicente Lorente; Salvador Petit; Julio Sahuquillo (ICS, 2022)

A Neural Network to Estimate Isolated Performance from Multi-Program Execution. - Manel Lurbe; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (PDP, 2022)

Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources. - Lucia Pons; Josué Feliu; José Puche; Chaoyi Huang; Salvador Petit; Julio Pons; María Engracia Gómez; Julio Sahuquillo (Future Gener. Comput. Syst., 2022)

VMT: Virtualized Multi-Threading for Accelerating Graph Workloads on Commodity Processors. - Josué Feliu; Ajeya Naithani; Julio Sahuquillo; Salvador Petit; Moinuddin K. Qureshi; Lieven Eeckhout (IEEE Trans. Computers, 2022)

DeepP: Deep Learning Multi-Program Prefetch Configuration for the IBM POWER 8. - Manel Lurbe; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (IEEE Trans. Computers, 2022)

Thread-to-Core Allocation in ARM Processors Building Synergistic Pairs. - Marta Navarro 001; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (PACT, 2023)

Stratus: A Hardware/Software Infrastructure for Controlled Cloud Research. - Lucia Pons; Salvador Petit; Julio Pons; María Engracia Gómez; Chaoyi Huang; Julio Sahuquillo (PDP, 2023)

Cloud White: Detecting and Estimating QoS Degradation of Latency-Critical Workloads in the Public Cloud. - Lucia Pons; Josué Feliu; Julio Sahuquillo; María Engracia Gómez; Salvador Petit; Julio Pons; Chaoyi Huang (Future Gener. Comput. Syst., 2023)

Main memory controller with multiple media technologies for big data workloads. - Miguel A. Avargues; Manel Lurbe; Salvador Petit; María Engracia Gómez; Rui Yang; Xiaoping Zhu; Guanhao Wang; Julio Sahuquillo (J. Big Data, 2023)

SYNPA: SMT Performance Analysis and Allocation of Threads to Cores in ARM Processors. - Marta Navarro 001; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (IPDPS, 2024)

Characterizing Power and Performance Interference Scalability in the 28-core ARM ThunderX2. - Ibai Calero; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (PDP, 2024)

A modular approach to build a hardware testbed for cloud resource management research. - Lucia Pons; Salvador Petit; Julio Pons; María Engracia Gómez; Julio Sahuquillo (J. Supercomput., 2024)

Smt efficiency in supervised ML methods: a throughput and interference analysis. - Lucia Pons; Marta Navarro 001; Salvador Petit; Julio Pons; María Engracia Gómez; Julio Sahuquillo (J. Big Data, 2024)

WAPA: A Workload-Agnostic CPI-Based Thread-to-Core Allocation Policy. - Marta Navarro 001; Vicent Pallardó-Julià; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (Euro-Par (1), 2025)

Power, energy, and performance analysis of single- and multi-threaded applications in the ARM ThunderX2. - Ibai Calero; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (J. Parallel Distributed Comput., 2025)

Advanced resource management: A hands-on master course in HPC and cloud computing. - Lucia Pons; Salvador Petit; Julio Sahuquillo (J. Parallel Distributed Comput., 2025)

TailBench++: Flexible Multi-Client, Multi-Server Benchmarking for Latency-Critical Workloads. - Zhilin Li; Lucia Pons; Salvador Petit; Julio Sahuquillo; Julio Pons (CoRR, 2025)

A New Family of Thread to Core Allocation Policies for an SMT ARM Processor. - Marta Navarro 001; Josué Feliu; Salvador Petit; María Engracia Gómez; Julio Sahuquillo (CoRR, 2025)

Dual Fast-Track Cache: Organizing Ring-Shaped Racetracks to Work as L1 Caches. - Alejandro Valero; Vicente Lorente; Salvador Petit; Julio Sahuquillo (IEEE Trans. Computers, 2025)