SOI Implementation of a 64-Bit Adder. - J. V. Tran; Farnaz Mounes-Toussi; S. N. Storino; D. L. Stasiak (ICCD, 1999)

A 0.2-μm, 1.8-V, SOI, 550-MHZ, 64-b PowerPC microprocessor with copper interconnects. - Anthony G. Aipperspach; David H. Allen; Dennis T. Cox; Nghia Phan; Salvatore N. Storino (IEEE J. Solid State Circuits, 1999)

A 440-ps 64-bit adder in 1.5-V/0.18-μm partially depleted SOI technology. - Daniel L. Stasiak; Farnaz Mounes-Toussi; Salvatore N. Storino (IEEE J. Solid State Circuits, 2001)

Fine-grained power managed dual-thread vector scalar unit for the first-generation CELL processor. - Tom Beacom; Timothy C. Buchholtz; D. Bradley; Jack Randolph; Salvatore N. Storino; Mark Veldhuizen; Sherman M. Dance; Jente B. Kuang; Steve Schwinn; Sue Cox; Fred Ziegler; J. Kao; et al. (CICC, 2005)

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation. - Gary S. Ditlow; Robert K. Montoye; Salvatore N. Storino; Sherman M. Dance; Sebastian Ehrenreich; Bruce M. Fleischer; Thomas W. Fox; Kyle M. Holmes; Junichi Mihara; Yutaka Nakamura; Shohji Onishi; Robert Shearer; et al. (ISSCC, 2011)