CTL based DFT solution to accelerate design to test development for system on chip devices. - Salvatore Talluto 001 (SoC, 2003)

Accurately Determining Bridging Defects from Layout. - Maria Gkatziani; Rohit Kapur; Qing Su; Ben Mathew; Roberto Mattiuzzo; Laura Tarantini; Cy Hay; Salvatore Talluto 001; Thomas W. Williams (DDECS, 2007)

State of the art low capture power methodology. - Swapnil Bahl; Roberto Mattiuzzo; Shray Khullar; Akhil Garg 001; S. Graniello; Khader S. Abdel-Hafez; Salvatore Talluto 001 (ITC, 2011)

Unifying scan compression. - Swapnil Bahl; Shreyans Rungta; Shray Khullar; Rohit Kapur; Anshuman Chandra; Salvatore Talluto 001; Pramod Notiyath; Ajay Rajagopalan (DFT, 2014)