A very wide bandwidth digital VCO using quadrature frequency multiplication and division implemented in AlGaAs/GaAs HBT's. - Pete M. Campbell; Hans J. Greub; Atul Garg; Sam A. Steidl; Steven R. Carlough; Matthew W. Ernest; Robert F. Philhower; Cliff A. Maier; Russell P. Kraft; John F. McDonald 001 (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy. - Atul Garg; Y. L. Le Coz; Hans J. Greub; R. B. Iverson; Robert F. Philhower; Pete M. Campbell; Cliff A. Maier; Sam A. Steidl; Matthew W. Ernest; Russell P. Kraft; Steven R. Carlough; J. W. Perry; et al. (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999)

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip. - Steven R. Carlough; Robert A. Philhower; Cliff A. Maier; Sam A. Steidl; Pete M. Campbell; Atul Garg; Kyung-Suc Nah; Matthew W. Ernest; James R. Loy; Thomas W. Krawczyk Jr.; Peter F. Curran; Russell P. Kraft; et al. (IEEE J. Solid State Circuits, 2000)

A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology. - Samuel A. Steidl; John F. McDonald 001 (IEEE J. Solid State Circuits, 2002)

A 39.8Gb/s to 43.1Gb/s SFI-5 compliant 16: 1 multiplexer and 1: 16 demultiplexer for optical communication systems. - Thomas W. Krawczyk Jr.; Sam A. Steidl; Richard Alexander; James Pulver; Gary Kowalski; Craig Hornbuckle; David Rowe (CICC, 2003)