XOR-Based Response Compactor Adaptive to X-Density Variation. - Samah Mohamed Saeed; Ozgur Sinanoglu (Asian Test Symposium, 2010)

Expedited response compaction for scan power reduction. - Samah Mohamed Saeed; Ozgur Sinanoglu (VTS, 2011)

DfT support for launch and capture power reduction in launch-off-capture testing. - Samah Mohamed Saeed; Ozgur Sinanoglu (ETS, 2012)

Multi-modal response compaction adaptive to x-density variation. - Samah Mohamed Saeed; Ozgur Sinanoglu (IET Comput. Digit. Tech., 2012)

Scan attack in presence of mode-reset countermeasure. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (IOLTS, 2013)

New scan-based attack using only the test mode. - Sk Subidh Ali; Ozgur Sinanoglu; Samah Mohamed Saeed; Ramesh Karri (VLSI-SoC, 2013)

New Scan-Based Attack Using Only the Test Mode and an Input Corruption Countermeasure. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (VLSI-SoC (Selected Papers), 2013)

Expedited-compact architecture for average scan power reduction. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Des. Test, 2013)

Predictive Techniques for Projecting Test Data Volume Compression. - Samah Mohamed Saeed; Ozgur Sinanoglu; Sobeeh Almukhaizim (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Slack removal for enhanced reliability and trust. - Abishek Ramdas; Samah Mohamed Saeed; Ozgur Sinanoglu (DTIS, 2014)

New scan attacks against state-of-the-art countermeasures and DFT. - Sk Subidh Ali; Ozgur Sinanoglu; Samah Mohamed Saeed; Ramesh Karri (HOST, 2014)

DfST: Design for secure testability. - Samah Mohamed Saeed (ITC, 2014)

Test-mode-only scan attack and countermeasure for contemporary scan architectures. - Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu; Ramesh Karri (ITC, 2014)

Design for Testability Support for Launch and Capture Power Reduction in Launch-Off-Shift and Launch-Off-Capture Testing. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Timing attack on NEMS relay based design of AES. - Samah Mohamed Saeed; Bodhisatwa Mazumdar; Sk Subidh Ali; Ozgur Sinanoglu (VLSI-SoC, 2015)

Novel Test-Mode-Only Scan Attack and Countermeasure for Compression-Based Scan Architectures. - Sk Subidh Ali; Samah Mohamed Saeed; Ozgur Sinanoglu; Ramesh Karri (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Activation of logic encrypted chips: Pre-test or post-test? - Muhammad Yasin; Samah Mohamed Saeed; Jeyavijayan Rajendran; Ozgur Sinanoglu (DATE, 2016)

Thwarting timing attacks on NEMS relay based designs. - Bodhisatwa Mazumdar; Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu (VTS, 2016)

Identifying Reversible Circuit Synthesis Approaches to Enable IP Piracy Attacks. - Samah Mohamed Saeed; Nithin Mahendran; Alwin Zulehner; Robert Wille; Ramesh Karri (ICCD, 2017)

Towards Reverse Engineering Reversible Logic. - Samah Mohamed Saeed; Xiaotong Cui; Robert Wille; Alwin Zulehner; Kaijie Wu 001; Rolf Drechsler; Ramesh Karri (CoRR, 2017)

A Comprehensive Design-for-Test Infrastructure in the Context of Security-Critical Applications. - Samah Mohamed Saeed; Ozgur Sinanoglu (IEEE Des. Test, 2017)

Timing Attack and Countermeasure on NEMS Relay Based Design of Block Ciphers. - Bodhisatwa Mazumdar; Samah Mohamed Saeed; Sk Subidh Ali; Ozgur Sinanoglu (IEEE Trans. Emerg. Top. Comput., 2017)

IC/IP piracy assessment of reversible logic. - Samah Mohamed Saeed; Xiaotong Cui; Alwin Zulehner; Robert Wille; Rolf Drechsler; Kaijie Wu 001; Ramesh Karri (ICCAD, 2018)

Identification of Synthesis Approaches for IP/IC Piracy of Reversible Circuits. - Samah Mohamed Saeed; Nithin Mahendran; Alwin Zulehner; Robert Wille; Ramesh Karri (ACM J. Emerg. Technol. Comput. Syst., 2019)

Locking the Design of Building Blocks for Quantum Circuits. - Samah Mohamed Saeed; Robert Wille; Ramesh Karri (ACM Trans. Embed. Comput. Syst., 2019)

CAD-Base: An Attack Vector into the Electronics Supply Chain. - Kanad Basu; Samah Mohamed Saeed; Christian Pilato; Mohammed Ashraf; Mohammed Thari Nabeel; Krishnendu Chakrabarty; Ramesh Karri (ACM Trans. Design Autom. Electr. Syst., 2019)

Reversible Circuits: IC/IP Piracy Attacks and Countermeasures. - Samah Mohamed Saeed; Alwin Zulehner; Robert Wille; Rolf Drechsler; Ramesh Karri (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Analysis of Test Data Tampering Attack on Manufacturing Testing. - Reginald Tetteh; Samah Mohamed Saeed (DTIS, 2020)

A Lightweight Approach to Detect Malicious/Unexpected Changes in the Error Rates of NISQ Computers. - Nikita Acharya; Samah Mohamed Saeed (ICCAD, 2020)

An Attack on Quantum Circuits Based on the Error Rates of NISQ Systems and a Countermeasure. - Nikita Acharya; Vedika Saravanan; Samah Mohamed Saeed (SVCC, 2020)

On the Difficulty of Inserting Trojans in Reversible Computing Architectures. - Xiaotong Cui; Samah Mohamed Saeed; Alwin Zulehner; Robert Wille; Kaijie Wu 001; Rolf Drechsler; Ramesh Karri (IEEE Trans. Emerg. Top. Comput., 2020)

Test Data-Driven Machine Learning Models for Reliable Quantum Circuit Output. - Vedika Saravanan; Samah Mohamed Saeed (ETS, 2021)

Decomposition-Based Watermarking of Quantum Circuits. - Vedika Saravanan; Samah Mohamed Saeed (ISQED, 2021)

Automated Flag Qubit Insertion for Reliable Quantum Circuit Output. - Nikita Acharya; Samah Mohamed Saeed (ISVLSI, 2021)

Graph Neural Networks for Idling Error Mitigation. - Vedika Servanan; Samah Mohamed Saeed (ICCAD, 2022)

Machine Learning for Quantum Hardware Performance Assessment. - Vedika Saravanan; Samah Mohamed Saeed (ICCD, 2022)

Towards Yield Improvement for AI Accelerators: Analysis and Exploration. - Mohammad Walid Charrwi; Huy Phan; Bo Yuan 001; Samah Mohamed Saeed (ISVLSI, 2022)

Pauli Error Propagation-Based Gate Reschedulingfor Quantum Circuit Error Mitigation. - Vedika Saravanan; Samah Mohamed Saeed (CoRR, 2022)

Test Points for Online Monitoring of Quantum Circuits. - Nikita Acharya; Miroslav Urbánek; Wibe A. de Jong; Samah Mohamed Saeed (ACM J. Emerg. Technol. Comput. Syst., 2022)

Revisiting Trojan Insertion Techniques for Post-Silicon Trojan Detection Evaluation. - Vedika Saravanan; Mohammad Walid Charrwi; Samah Mohamed Saeed (ISVLSI, 2023)

Data-Driven Reliability Models of Quantum Circuit: From Traditional ML to Graph Neural Network. - Vedika Saravanan; Samah Mohamed Saeed (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Time-Aware Re-Synthesis for Secure Quantum Systems. - Christian Rasmussen; Samah Mohamed Saeed (HOST, 2024)

Can ML-Based Reliability Models Span Quantum Hardware Boundaries? - Georgios Ioannou; Gopika Kizhuvettil; Mohammad Walid Charrwi; Samah Mohamed Saeed (ISVLSI, 2024)

Quantum Circuit Partitioning for Scalable Noise-Aware Quantum Circuit Re-Synthesis. - Mohammad Walid Charrwi; Georgios Ioannou; Ed Younis; Wibe Albert de Jong; Samah Mohamed Saeed (QCE, 2024)

Noise Adaptive Quantum Circuit Mapping Using Reinforcement Learning and Graph Neural Network. - Vedika Saravanan; Samah Mohamed Saeed (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Don't Cares in Quantum Circuits: A Security Perspective. - Donald Lushi; Christian Rasmussen; Samah Mohamed Ahmed Saeed (ACM Great Lakes Symposium on VLSI, 2025)

Undermining Quantum Circuit Obfuscation: Insights from Structural Analysis. - Donald Lushi; Samah Mohamed Saeed (HOST, 2025)