Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic. - Gopal Paul; Sambhu Nath Pradhan; Ajit Pal; Bhargab B. Bhattacharya (APCCAS, 2006)

Three-level AND-OR-XOR network synthesis: A GA based approach. - Sambhu Nath Pradhan; M. Tilak Kumar; Santanu Chattopadhyay (APCCAS, 2008)

AND-XOR Network Synthesis with Area-Power Trade-off. - Sambhu Nath Pradhan; Santanu Chattopadhyay (ICIIS, 2008)

Integrated Power-Gating and State Assignment for Low Power FSM Synthesis. - Sambhu Nath Pradhan; M. Tilak Kumar; Santanu Chattopadhyay (ISVLSI, 2008)

Low power finite state machine synthesis using power-gating. - Sambhu Nath Pradhan; M. Tilak Kumar; Santanu Chattopadhyay (Integr., 2011)

And-or-XOR Network Synthesis with Area-Power Trade-Off. - Sambhu Nath Pradhan; M. Tilak Kumar; Santanu Chattopadhyay (J. Circuits Syst. Comput., 2011)

A technique for power reduction of CMOS circuit at 65nm technology. - Angshuman Chakraborty; Sambhu Nath Pradhan (RAIT, 2012)

Power Modeling of Power Gated FSM and Its Low Power Realization by Simultaneous Partitioning and State Encoding Using Genetic Algorithm. - Priyanka Choudhury; Sambhu Nath Pradhan (VDAT, 2012)

Multiplexer-Based Multi-Level Circuit Synthesis with Area-Power Trade-Off. - Sambhu Nath Pradhan; Santanu Chattopadhyay (J. Circuits Syst. Comput., 2012)

An Approach for Low Power Design of Power Gated Finite State Machines Considering Partitioning and State Encoding Together. - Priyanka Choudhury; Sambhu Nath Pradhan (J. Low Power Electron., 2012)

Power Reduction by Integrated Within_Clock_Power Gating and Power Gating (WCPG_in_PG). - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (VDAT, 2013)

Gate level leakage minimisation at 90 nm technology. - Angshuman Chakraborty; Sambhu Nath Pradhan (Int. J. Comput. Aided Eng. Technol., 2013)

Power gating architecture implementation inside clock period to reduce power. - Debanjali Nath; Priyanka Choudhury; Abhishek Nag; Sambhu Nath Pradhan (Int. J. Comput. Aided Eng. Technol., 2014)

Thermal aware FPRM based AND-XOR network synthesis of logic circuits. - Apangshu Das; Sambhu Nath Pradhan (ReTIS, 2015)

Thermal aware AND-OR-XOR network synthesis. - Priyanka Choudhury; Debanjali Nath; Vivek Rai; Sambhu Nath Pradhan (VDAT, 2015)

Layout-oriented look up table-based dual threshold approach to reduce leakage. - Sambhu Nath Pradhan; Angshuman Chakraborty; Abhishek Nag; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2015)

An Autonomous Clock Gating Technique in Finite State Machines Based on Registers Partitioning. - Abhishek Nag; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2016)

Hybrid Approach of Within-Clock Power Gating and Normal Power Gating to Reduce Power. - Debanjali Nath; Priyanka Choudhury; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2016)

Shared Reed-Muller Decision Diagram Based Thermal-Aware AND-XOR Decomposition of Logic Circuits. - Apangshu Das; Sambhu Nath Pradhan (VLSI Design, 2016)

Transistor level realisation of power gated FSM. - Sambhu Nath Pradhan; Priyanka Choudhury; Debanjali Nath (Int. J. Comput. Aided Eng. Technol., 2017)

Leakage Reduction of SRAM-Based Look-Up Table Using Dynamic Power Gating. - Abhishek Nag; Debanjali Nath; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2017)

Facial expression recognition based on eigenspaces and principle component analysis. - Ashim Saha; Sambhu Nath Pradhan (Int. J. Comput. Vis. Robotics, 2018)

DOTFloor-A Diffusion Oriented Time-Improved Floorplanner for Macrocells. - Somnath Roy Choudhury; Sambhu Nath Pradhan (IEEE Access, 2019)

Thermal-Aware Partitioning and Encoding of Power-Gated FSM. - Priyanka Choudhury; Kanchan Manna; Vivek Rai; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2019)

Low-Power FSM Synthesis Based on Automated Power and Clock Gating Technique. - Abhishek Nag; Subhajit Das 004; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2019)

An Improved Matrix Generation Framework for Thermal Aware Placement in VLSI. - Somnath Roy Choudhury; Sambhu Nath Pradhan (IEEE Access, 2020)

FPGA and ASIC realisation of EMD algorithm for real-time signal processing. - Kaushik Das; Debanjali Nath; Sambhu Nath Pradhan (IET Circuits Devices Syst., 2020)

An efficient hardware realization of EMD for real-time signal processing applications. - Kaushik Das; Sambhu Nath Pradhan (Int. J. Circuit Theory Appl., 2020)

Low power transistor level synthesis of finite state machines using a novel dual gating technique. - Abhishek Nag; Subhajit Das 004; Sambhu Nath Pradhan (Int. J. Embed. Syst., 2020)

An Elitist Non-Dominated Multi-Objective Genetic Algorithm Based Temperature Aware Circuit Synthesis. - Apangshu Das; Sambhu Nath Pradhan (Int. J. Interact. Multim. Artif. Intell., 2020)

NSGA-II Based Thermal-Aware Mixed Polarity Dual Reed-Muller Network Synthesis Using Parallel Tabular Technique. - Apangshu Das; Yallapragada C. Hareesh; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2020)

Lookup table-based negative-bias temperature instability effect and leakage power co-optimization using genetic algorithm approach. - Abhishek Bhattacharjee; Dheeraj Kumar Sahu; Sambhu Nath Pradhan (Int. J. Circuit Theory Appl., 2021)

Field-programmable gate array-based design for real-time computation of ensemble empirical mode decomposition. - Kaushik Das; Sambhu Nath Pradhan (Int. J. Circuit Theory Appl., 2021)

NBTI-Aware Power Gating Design with Dynamically Varying Stress Probability Control on Sleep Transistor. - Abhishek Bhattacharjee; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2021)

IoT Based Design of Air Quality Monitoring System Web Server for Android Platform. - Koel Datta Purkayastha; Ritesh Kishore Mishra; Arunava Shil; Sambhu Nath Pradhan (Wirel. Pers. Commun., 2021)

Design of Power Gated SRAM Cell for Reducing the NBTI Effect and Leakage Power Dissipation During the Hold Operation. - Abhishek Bhattacharjee; Abhishek Nag; Kaushik Das; Sambhu Nath Pradhan (J. Electron. Test., 2022)

Shared reduced ordered binary decision diagram-based thermal-aware network synthesis. - Apangshu Das; Vivek Kumar Singh; Sambhu Nath Pradhan (Int. J. Circuit Theory Appl., 2022)

Design and analysis of a low power strategy in finite state machines implemented in configurable logic blocks. - Vivek Kumar Singh; Abhishek Nag; Sambhu Nath Pradhan (Int. J. Embed. Syst., 2022)

Hardware architecture design for complementary ensemble empirical mode decomposition algorithm. - Kaushik Das; Sambhu Nath Pradhan (Integr., 2023)

Design and Lifetime Estimation of Low-Power 6-Input Look-Up Table Used in Modern FPGA. - Vivek Kumar Singh; Abhishek Nag; Abhishek Bhattacharjee; Sambhu Nath Pradhan (J. Circuits Syst. Comput., 2023)

Area-time-energy efficient architecture of CBNS-based fast Fourier transform. - Kaushik Das; Eda Harshavardhan Reddy; Arpita Mandal; Sambhu Nath Pradhan; Abhishek Bhattacharjee (Int. J. Circuit Theory Appl., 2024)

Efficient Hardware Architecture Design of Radix-22 Fast Fourier Transform Using Coordinate Rotation Digital Computer. - Kaushik Das; Sambhu Nath Pradhan; Abhishek Bhattacharjee (J. Circuits Syst. Comput., 2024)