Concurrent logic and interconnect delay estimation of MOS circuits by mixed algebraic and Boolean symbolic analysis. - Sambuddha Bhattacharya; Chuanjin Richard Shi (ISCAS (4), 2003)

Automatic analog layout retargeting for new processes and device sizes. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (ISCAS (4), 2003)

IPRAIL - intellectual property reuse-based analog IC layout automation. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (Integr., 2003)

Hierarchical extraction and verification of symmetry constraints for analog layout automation. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Roy Hartono; Chuanjin Richard Shi (ASP-DAC, 2004)

Multiple specifications radio-frequency integrated circuit design with automatic template-driven layout retargeting. - Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Roy Hartono; Chuanjin Richard Shi (ASP-DAC, 2004)

CrtSmile: a CAD tool for CMOS RF transistor substrate modeling incorporating layout effects. - Zhao Li; Ravikanth Suravarapu; Roy Hartono; Sambuddha Bhattacharya; Kartikeya Mayaram; Chuanjin Richard Shi (ASP-DAC, 2004)

Correct-by-construction layout-centric retargeting of large analog designs. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Roy Hartono; Chuanjin Richard Shi (DAC, 2004)

Template-driven parasitic-aware optimization of analog integrated circuit layouts. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Chuanjin Richard Shi (DAC, 2005)

Automatic Device Layout Generation for Analog Layout Retargeting. - Roy Hartono; Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Chuanjin Richard Shi (VLSI Design, 2005)

Template-based parasitic-aware optimization and retargeting of analog and RF integrated circuit layouts. - Nuttorn Jangkrajarng; Lihong Zhang; Sambuddha Bhattacharya; Nathan Kohagen; Chuanjin Richard Shi (ICCAD, 2006)

Multilevel symmetry-constraint generation for retargeting large analog layouts. - Sambuddha Bhattacharya; Nuttorn Jangkrajarng; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

Cell Swapping Based Migration Methodology for Analog and Custom Layouts. - Shabbir H. Batterywala; Sambuddha Bhattacharya; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

On Efficient and Robust Constraint Generation for Practical Layout Legalization. - Sambuddha Bhattacharya; Shabbir H. Batterywala; Subramanian Rajagopalan; Hi-Keung Tony Ma; Narendra V. Shenoy (ISQED, 2008)

Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach. - Lihong Zhang; Nuttorn Jangkrajarng; Sambuddha Bhattacharya; Chuanjin Richard Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Efficient Analog/RF Layout Closure with Compaction Based Legalization. - Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSI Design, 2009)

Automatic design rule correction in presence of multiple grids and track patterns. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (DAC, 2013)

Fixing Double Patterning violations with look-ahead. - Sambuddha Bhattacharya; Subramanian Rajagopalan; Shabbir H. Batterywala (ASP-DAC, 2014)

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple Grids. - Nitin Salodkar; Subramanian Rajagopalan; Sambuddha Bhattacharya; Shabbir H. Batterywala (VLSID, 2015)

AMuSE: Attentive Multilingual Speech Encoding for Zero-Prior ASR. - Ashutosh Varshney; Debmalya Chakrabarty; Akshat Jaiswal; Harish Arsikere; Abhinav Jain; Swayambhu Nath Ray; Frederick Weber; Anand Mohan; Prantik Sen; Garima Lalwani; Sambuddha Bhattacharya; Sri Garimella (ICASSP, 2025)