Efficient FPGA based architecture for high-order FIR filtering using simultaneous DSP and LUT reduced utilization. - Mountassar Maamoun; Adnane Hassani; Samir Dahmani; Hocine Ait Saadi; Ghania Zerari; Noureddine Chabini; Rachid Beguenane (IET Circuits Devices Syst., 2021)

An Efficient FPGA-Based Gaussian Random Number Generator Using an Accurate Segmented Box-Muller Method. - Samir Dahmani; Mountassar Maamoun; Ghania Zerari; Noureddine Chabini; Rachid Beguenane (IEEE Access, 2023)