Analytical and numerical analyses of the delay time of BiCMOS structures. - Samir S. Rofail; Mohamed I. Elmasry (IEEE J. Solid State Circuits, 1992)

Analysis of latchup and parasitic effects in merged BiCMOS structures. - Samir S. Rofail; Mohamed I. Elmasry (IEEE J. Solid State Circuits, 1993)

Schottky merged BiCMOS structures. - Samir S. Rofail; Mohamed I. Elmasry (IEEE J. Solid State Circuits, 1994)

Low-voltage, low-power BiCMOS digital circuits. - Samir S. Rofail (IEEE J. Solid State Circuits, 1994)

A charge-trapping-based technique to design low-voltage BiCMOS logic circuits. - Kiat Seng Yeo; Samir S. Rofail (IEEE J. Solid State Circuits, 1998)

A low-power 16×16-b parallel multiplier utilizing pass-transistor logic. - Chong-Fatt Law; Samir S. Rofail; Kiat Seng Yeo (IEEE J. Solid State Circuits, 1999)