Deriving Pipeline Models for Timing Analysis from High-Level HDL Processor Designs. - Samira Ait Bensaid; Mihail Asavoae; Farhat Thabet; Mathieu Jan (MEMOCODE, 2022)

Work in Progress: Automatic Construction of Pipeline Datapaths from High-Level HDL Code. - Samira Ait Bensaid; Mihail Asavoae; Farhat Thabet; Mathieu Jan (RTAS, 2022)

Formal Semantics of Hardware Compilation Framework. (Sémantique formelle d'une infrastructure de compilation matériel). - Samira Ait Bensaid (2023)