Multi Replica Bitline Delay Technique for Variation Tolerant Timing of SRAM Sense Amplifiers. - Samira Ataei; James E. Stine (ACM Great Lakes Symposium on VLSI, 2015)

A differential single-port 8T SRAM bitcell for variability tolerance and low voltage operation. - Samira Ataei; James E. Stine (IGSC, 2015)

OpenRAM: an open-source memory compiler. - Matthew R. Guthaus; James E. Stine; Samira Ataei; Brian Chen; Bin Wu; Mehedi Sarwar (ICCAD, 2016)

A 64 kb differential single-port 12T SRAM design with a bit-interleaving scheme for low-voltage operation in 32 nm SOI CMOS. - Samira Ataei; James E. Stine; Matthew R. Guthaus (ICCD, 2016)

A Reconfigurable Replica Bitline to Determine Optimum SRAM Sense Amplifier Set Time. - Samira Ataei; James E. Stine (ACM Great Lakes Symposium on VLSI, 2017)

WIP. Open-source standard cell characterization process flow on 45 nm (FreePDK45), 0.18 µm, 0.25 µm, 0.35 µm and 0.5 µm. - Rabin Thapa; Samira Ataei; James E. Stine (MSE, 2017)

A high performance multi-port SRAM for low voltage shared memory systems in 32 nm CMOS. - Samira Ataei; Matthew Gaalswyk; James E. Stine (MWSCAS, 2017)

A Methodology for Low-Power Approximate Embedded SRAM Within Multimedia Applications. - Samira Ataei; James E. Stine (SoCC, 2018)

A 64 kB Approximate SRAM Architecture for Low-Power Video Applications. - Samira Ataei; James E. Stine (IEEE Embed. Syst. Lett., 2018)

AMC: An Asynchronous Memory Compiler. - Samira Ataei; Rajit Manohar (ASYNC, 2019)

Shared-Staticizer for Area-Efficient Asynchronous Circuits. - Samira Ataei; Rajit Manohar (ASYNC, 2020)

An Open-Source EDA Flow for Asynchronous Logic. - Samira Ataei; Wenmian Hua; Yihang Yang; Rajit Manohar; Yi-Shan Lu; Jiayuan He 003; Sepideh Maleki; Keshav Pingali (IEEE Des. Test, 2021)