An FPGA implementation of the simplex algorithm. - Samuel Bayliss; Christos-Savvas Bouganis; George A. Constantinides; Wayne Luk (FPT, 2006)

Application Specific Memory Access, Reuse and Reordering for SDRAM. - Samuel Bayliss; George A. Constantinides (ARC, 2011)

Optimizing SDRAM bandwidth for custom FPGA loop accelerators. - Samuel Bayliss; George A. Constantinides (FPGA, 2012)

Analytical synthesis of bandwidth-efficient SDRAM address generators. - Samuel Bayliss; George A. Constantinides (Microprocess. Microsystems, 2012)

FPGA-based K-means clustering using tree-based data structures. - Felix Winterstein; Samuel Bayliss; George A. Constantinides (FPL, 2013)

SOAP: Structural optimization of arithmetic expressions for high-level synthesis. - Xitong Gao; Samuel Bayliss; George A. Constantinides (FPT, 2013)

High-level synthesis of dynamic data structures: A case study using Vivado HLS. - Felix Winterstein; Samuel Bayliss; George A. Constantinides (FPT, 2013)

GPU vs FPGA: A Comparative Analysis for Non-standard Precision. - Umar Ibrahim Minhas; Samuel Bayliss; George A. Constantinides (ARC, 2014)

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs. - Kan Shi; David Boland; Edward A. Stott; Samuel Bayliss; George A. Constantinides (DAC, 2014)

Compiling Higher Order Functional Programs to Composable Digital Hardware. - Eduardo Aguilar-Pelaez; Samuel Bayliss; Alex I. Smith; Felix Winterstein; Dan R. Ghica; David B. Thomas; George A. Constantinides (FCCM, 2014)

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis. - Felix Winterstein; Samuel Bayliss; George A. Constantinides (FCCM, 2014)

Area implications of memory partitioning for high-level synthesis on FPGAs. - Luca Gallo; Alessandro Cilardo; David B. Thomas; Samuel Bayliss; George A. Constantinides (FPL, 2014)

Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS. - Junyi Liu; Samuel Bayliss; George A. Constantinides (FCCM, 2015)

MATCHUP: Memory Abstractions for Heap Manipulating Programs. - Felix Winterstein; Kermin Fleming; Hsin-Jung Yang; Samuel Bayliss; George A. Constantinides (FPGA, 2015)

Survey of domain-specific languages for FPGA computing. - Nachiket Kapre; Samuel Bayliss (FPL, 2016)

Separation Logic for High-Level Synthesis. - Felix J. Winterstein; Samuel R. Bayliss; George A. Constantinides (ACM Trans. Reconfigurable Technol. Syst., 2016)

Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies. - Junyi Liu; John Wickerson; Samuel Bayliss; George A. Constantinides (ACSSC, 2017)

Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis. - Junyi Liu; John Wickerson; Samuel Bayliss; George A. Constantinides (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Vyasa: A High-Performance Vectorizing Compiler for Tensor Convolutions on the Xilinx AI Engine. - Prasanth Chatarasi; Stephen Neuendorffer; Samuel Bayliss; Kees A. Vissers; Vivek Sarkar (HPEC, 2020)

Efficiency, Expressivity, and Extensibility in a Close-to-Metal NPU Programming Interface. - Erika Hunhoff; Joseph Melber; Kristof Denolf; Andra Bisca; Samuel Bayliss; Stephen Neuendorffer; Jeff Fifield; Jack Lo; Pranathi Vasireddy; Phil James-Roxby; Eric Keller (FCCM, 2025)

From Loop Nests to Silicon: Mapping AI Workloads onto AMD NPUs with MLIR-AIR. - Erwei Wang; Samuel Bayliss; Andra Bisca; Zachary Blair; Sangeeta Chowdhary; Kristof Denolf; Jeff Fifield; Brandon Freiberger; Erika Hunhoff; Phil James-Roxby; Jack Lo; Joseph Melber; et al. (CoRR, 2025)