Automated derivation of NoC Communication Specifications from Application Constraints. - Samuel Evain; Jean-Philippe Diguet; Milad El Khodary; Dominique Houzet (SiPS, 2006)

NoC Design Flow for TDMA and QoS Management in a GALS Context. - Samuel Evain; Jean-Philippe Diguet; Dominique Houzet (EURASIP J. Embed. Syst., 2006)

Efficient space-time noc path allocation based on mutual exclusion and pre-reservation. - Samuel Evain; Jean-Philippe Diguet (ACM Great Lakes Symposium on VLSI, 2007)

NOC-centric Security of Reconfigurable SoC. - Jean-Philippe Diguet; Samuel Evain; Romain Vaslin; Guy Gogniat; Emmanuel Juin (NOCS, 2007)

System-level hardware-based protection of memories against soft-errors. - Valentin Gherman; Samuel Evain; Mickael Cartron; Nathaniel Seymour; Yannick Bonhomme (DATE, 2009)

Programmable restricted SEC codes to mask permanent faults in semiconductor memories. - Samuel Evain; Yannick Bonhomme; Valentin Gherman (IOLTS, 2010)

Error prediction based on concurrent self-test and reduced slack time. - Valentin Gherman; J. Massas; Samuel Evain; Stéphane Chevobbe; Yannick Bonhomme (DATE, 2011)

Generalized parity-check matrices for SEC-DED codes with fixed parity. - Valentin Gherman; Samuel Evain; Nathaniel Seymour; Yannick Bonhomme (IOLTS, 2011)

Programmable extended SEC-DED codes for memory errors. - Valentin Gherman; Samuel Evain; Fabrice Auzanneau; Yannick Bonhomme (VTS, 2011)

Memory reliability improvements based on maximized error-correcting codes. - Valentin Gherman; Samuel Evain; Yannick Bonhomme (ETS, 2012)

Scan design with shadow flip-flops for low performance overhead and concurrent delay fault detection. - Sébastien Sarrazin; Samuel Evain; Lirida Alves de Barros Naviner; Yannick Bonhomme; Valentin Gherman (DATE, 2013)

Error-correction schemes with erasure information for fast memories. - Samuel Evain; Valentin Gherman (ETS, 2013)

Memory Reliability Improvement Based on Maximized Error-Correcting Codes. - Valentin Gherman; Samuel Evain; Yannick Bonhomme (J. Electron. Test., 2013)

Shadow-scan design with low latency overhead and in-situ slack-time monitoring. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Alexandre Valentian; Suresh Pajaniradja; Lirida Alves de Barros Naviner; Valentin Gherman (ETS, 2014)

Flip-flop selection for in-situ slack-time monitoring based on the activation probability of timing-critical paths. - Sébastien Sarrazin; Samuel Evain; Ivan Miro Panades; Lirida Alves de Barros Naviner; Valentin Gherman (IOLTS, 2014)

Error Correction Schemes with Erasure Information for Fast Memories. - Samuel Evain; Valentin Savin; Valentin Gherman (J. Electron. Test., 2014)

Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities. - Valentin Gherman; Samuel Evain; Bastien Giraud (DATE, 2020)