Fully depleted CMOS/SOI device design guidelines for low power applications. - Srinivasa R. Banna; Philip C. H. Chan; Mansun Chan; Samuel K. H. Fung; Ping K. Ko (ISLPED, 1997)

BSIMPD: a partial-depletion SOI MOSFET model for deep-submicron CMOS designs. - Pin Su; Samuel K. H. Fung; Stephen Tang; Fariborz Assaderaghi; Chenming Hu (CICC, 2000)

PD/SOI SRAM performance in presence of gate-to-body tunneling current. - Rajiv V. Joshi; Ching-Te Chuang; Samuel K. H. Fung; Fari Assaderaghi; Melanie Sherony; I. Yang; Ghavam V. Shahidi (IEEE Trans. Very Large Scale Integr. Syst., 2003)