Synthesis of threshold logic circuits using tree matching. - Tejaswi Gowda; Samuel Leshner; Sarma B. K. Vrudhula; Goran Konjevod (ECCTD, 2007)

Threshold Logic Gene Regulatory Model - Prediction of Dorsal-ventral Patterning and Hardware-based Simulation of Drosophila. - Tejaswi Gowda; Samuel Leshner; Sarma B. K. Vrudhula; Seungchan Kim (BIODEVICES (1), 2008)

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS. - Samuel Leshner; Krzysztof S. Berezowski; Xiaoyin Yao; Gayathri Chalivendra; Saurabh Patel; Sarma B. K. Vrudhula (ISVLSI, 2010)

Low power ARM® Cortex™-M0 CPU and SRAM using Deeply Depleted Channel (DDC) transistors with Vdd scaling and body bias. - Vineet Agrawal; N. Kepler; David Kidd; Gokul Krishnan; Samuel Leshner; T. Bakishev; D. Zhao; P. Ranade; R. Roy; M. Wojko; Lawrence T. Clark; Robert Rogenmoser; et al. (CICC, 2013)

SRAM cell optimization for low AVT transistors. - Lawrence T. Clark; Samuel Leshner; George Tien (ISLPED, 2013)

Independent N and P process monitors for body bias based process corner correction. - Lawrence T. Clark; David Kidd; Vineet Agrawal; Samuel Leshner; Gokul Krishnan (CICC, 2014)