Statistical clock skew modeling with data delay variations. - David M. Harris; Sam Naffziger (IEEE Trans. Very Large Scale Integr. Syst., 2001)

The implementation of the Itanium 2 microprocessor. - Samuel D. Naffziger; Glenn Colón-Bonet; Timothy C. Fischer; Reid J. Riedlinger; Thomas J. Sullivan; Tom Grutkowski (IEEE J. Solid State Circuits, 2002)

Correction to "statistical clock skew modeling with data delay variations". - David M. Harris; Sam Naffziger (IEEE Trans. Very Large Scale Integr. Syst., 2003)

A 90-nm variable frequency clock system for a power-managed itanium architecture processor. - Tim C. Fischer; Jayen Desai; Bruce Andrew Doyle; Samuel Naffziger; Ben Patella (IEEE J. Solid State Circuits, 2006)

Power and temperature control on a 90-nm Itanium family processor. - Rich McGowen; Christopher Poirier; Chris Bostak; Jim Ignowski; Mark Millican; Warren H. Parks; Samuel Naffziger (IEEE J. Solid State Circuits, 2006)

The implementation of a 2-core, multi-threaded itanium family processor. - Samuel Naffziger; Blaine A. Stackhouse; Tom Grutkowski; Doug Josephson; Jayen Desai; Elad Alon; Mark Horowitz (IEEE J. Solid State Circuits, 2006)

An x86-64 core implemented in 32nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Greg Constant; Amy Novak; Sam Naffziger (ISSCC, 2010)

A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm2 at 81% efficiency. - Hanh-Phuc Le; Michael D. Seeman; Seth Sanders; Visvesh S. Sathe 001; Samuel Naffziger; Elad Alon (ISSCC, 2010)

Design solutions for the Bulldozer 32nm SOI 2-core processor module in an 8-core CPU. - Tim C. Fischer; Srikanth Arekapudi; Eric Busta; Carl Dietz; Michael Golden; Scott Hilker; Aaron Horiuchi; Kevin A. Hurd; Dave Johnson 002; Hugh McIntyre; Samuel Naffziger; James Vinh; et al. (ISSCC, 2011)

An x86-64 Core in 32 nm SOI CMOS. - Ravi Jotwani; Sriram Sundaram; Stephen Kosonocky; Alex Schaefer; Victor Andrade; Amy Novak; Sam Naffziger (IEEE J. Solid State Circuits, 2011)

Design and implementation of soft-edge flip-flops for x86-64 AMD microprocessor modules. - Steve J. Dillen; Donald A. Priore; Aaron Horiuchi; Samuel Naffziger (CICC, 2012)

Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS. - Hugh McIntyre; Srikanth Arekapudi; Eric Busta; Timothy C. Fischer; Michael Golden; Aaron Horiuchi; Tom Meneghini; Samuel Naffziger; James Vinh (IEEE J. Solid State Circuits, 2012)

Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. - Visvesh S. Sathe 001; Srikanth Arekapudi; Alexander T. Ishii; Charles Ouyang; Marios C. Papaefthymiou; Samuel Naffziger (IEEE J. Solid State Circuits, 2013)

AMD SOC power management: Improving performance/watt using run-time feedback. - William Lloyd Bircher; Sam Naffziger (CICC, 2014)

Welcome program chairs. - Samuel Naffziger; Guri Sohi (Hot Chips Symposium, 2014)

5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor. - Aaron Grenat; Sanjay Pant; Ravinder Rachala; Samuel Naffziger (ISSCC, 2014)

4.8 A 28nm x86 APU optimized for power and area efficiency. - Kathryn Wilcox; David Akeson; Harry R. Fair III; Jim Farrell; Dave Johnson 002; Guhan Krishnan; Hugh McIntyre; Edward McLellan; Samuel Naffziger; Russell Schreiber; Sriram Sundaram; Jonathan White (ISSCC, 2015)

Steamroller Module and Adaptive Clocking System in 28 nm CMOS. - Kathryn Wilcox; Robert Cole; Harry R. Fair III; Kevin Gillespie; Aaron Grenat; Carson Henrion; Ravi Jotwani; Stephen Kosonocky; Benjamin Munger; Samuel Naffziger; Robert S. Orefice; Sanjay Pant; et al. (IEEE J. Solid State Circuits, 2015)

Hot Chips 26 [Guest editors' introduction]. - Samuel Naffziger; Guri Sohi (IEEE Micro, 2015)

Unified Power Frequency Model Framework. - Sriram Sundaram; Warren He; Sriram Sambamurthy; Aaron Grenat; Steven Liepe; Samuel Naffziger (ISLPED, 2016)

4.2 Increasing the performance of a 28nm x86-64 microprocessor through system power management. - Aaron Grenat; Sriram Sundaram; Stephen Kosonocky; Ravinder Rachala; Sriram Sambamurthy; Steven Liepe; Miguel Rodriguez; Tom Burd; Adam Clark; Michael Austin; Samuel Naffziger (ISSCC, 2016)

Adaptive Voltage Frequency Scaling Using Critical Path Accumulator Implemented in 28nm CPU. - Sriram Sundaram; Sriram Sambamurthy; Michael Austin; Aaron Grenat; Michael Golden; Stephen Kosonocky; Samuel Naffziger (VLSID, 2016)

Carrizo: A High Performance, Energy Efficient 28 nm APU. - Benjamin Munger; David Akeson; Srikanth Arekapudi; Tom Burd; Harry R. Fair III; Jim Farrell; Dave Johnson 002; Guhan Krishnan; Hugh McIntyre; Edward McLellan; Samuel Naffziger; Russell Schreiber; et al. (IEEE J. Solid State Circuits, 2016)

Energy-Efficient Graphics and Multimedia in 28-nm Carrizo Accelerated Processing Unit. - Guhan Krishnan; Dan Bouvier; Samuel Naffziger (IEEE Micro, 2016)

Bristol Ridge: A 28-nm × 86 Performance-Enhanced Microprocessor Through System Power Management. - Sriram Sundaram; Aaron Grenat; Samuel Naffziger; Tom Burd; Stephen Kosonocky; Steven Liepe; Ravinder Rachala; Miguel Rodriguez; Michael Austin; Sriram Sambamurthy (IEEE J. Solid State Circuits, 2017)

'Zeppelin': An SoC for multichip architectures. - Noah Beck; Sean White; Milam Paraschou; Samuel Naffziger (ISSCC, 2018)

Zen: An Energy-Efficient High-Performance × 86 Core. - Teja Singh; Alex Schaefer; Sundar Rangarajan; Deepesh John; Carson Henrion; Russell Schreiber; Miguel Rodriguez; Stephen Kosonocky; Samuel Naffziger; Amy Novak (IEEE J. Solid State Circuits, 2018)

"Zeppelin": An SoC for Multichip Architectures. - Thomas Burd; Noah Beck; Sean White; Milam Paraschou; Nathan Kalyanasundharam; Gregg Donley; Alan Smith 003; Larry Hewitt; Samuel Naffziger (IEEE J. Solid State Circuits, 2019)

8.4 Radeon RX 5700 Series: The AMD 7nm Energy-Efficient High-Performance GPUs. - Sal Dasgupta; Teja Singh; Ashish Jain; Samuel Naffziger; Deepesh John; Chetan Bisht; Pradeep Jayaraman (ISSCC, 2020)

2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. - Samuel Naffziger; Kevin Lepak; Milam Paraschou; Mahesh Subramony (ISSCC, 2020)

Understanding Chiplets Today to Anticipate Future Integration Opportunities and Limits. - Gabriel H. Loh; Samuel Naffziger; Kevin Lepak (DATE, 2021)

Pioneering Chiplet Technology and Design for the AMD EPYC™ and Ryzen™ Processor Families : Industrial Product. - Samuel Naffziger; Noah Beck; Thomas Burd; Kevin Lepak; Gabriel H. Loh; Mahesh Subramony; Sean White (ISCA, 2021)

SE1: What Technologies Will Shape the Future of Computing? - Hugh Mair; Shinichiro Shiratake; Eric Karl; Thomas Burd; Jonathan Chang; Debbie Marr; Samuel Naffziger; Henk Corporaal; Ken Takeuchi; Naresh R. Shanbhag (ISSCC, 2021)

A New Era of Tailored Computing. - Mark Papermaster; Stephen Kosonocky; Gabriel H. Loh; Samuel Naffziger (VLSI Circuits, 2021)

3D V-Cache: the Implementation of a Hybrid-Bonded 64MB Stacked Cache for a 7nm x86-64 CPU. - John J. Wuu; Rahul Agarwal; Michael Ciraula; Carl Dietz; Brett Johnson; Dave Johnson 002; Russell Schreiber; Raja Swaminathan; Will Walker; Samuel Naffziger (ISSCC, 2022)

Innovation For the Next Decade of Compute Efficiency. - Lisa Su; Sam Naffziger (ISSCC, 2023)

Realizing the AMD Exascale Heterogeneous Processor Vision : Industry Product. - Alan Smith 003; Gabriel H. Loh; Michael J. Schulte; Mike Ignatowski; Samuel Naffziger; Mike Mantor; Nathan Kalyanasundharam; Vamsi Alla; Nicholas Malaya; Joseph L. Greathouse; Eric Chapman; Raja Swaminathan (ISCA, 2024)

AMD Instinct™ MI300X Accelerator: Packaging and Architecture Co-Optimization. - Alan Smith 003; Gabriel H. Loh; John J. Wuu; Samuel Naffziger; Tyrone Huang; Hugh McIntyre; Ramon Mangaser; Wonjun Jung; Raja Swaminathan (VLSI Technology and Circuits, 2024)

Interconnect Design for Heterogeneous Integration of Chiplets in the AMD Instinct MI300X Accelerator. - Alan Smith 003; Gabriel H. Loh; Samuel Naffziger; John J. Wuu; Nathan Kalyanasundharam; Eric Chapman; Raja Swaminathan; Tyrone Huang; Wonjun Jung; Alexander Kaganov; Hugh McIntyre; Ramon Mangaser (IEEE Micro, 2025)