Evaluating coverage collection using the VEasy functional verification tool suite. - Samuel Nascimento Pagliarini; Paulo André Haacke; Fernanda Lima Kastensmidt (LATW, 2011)

VEasy: A tool suite for teaching VLSI functional verification. - Samuel Nascimento Pagliarini; Fernanda Lima Kastensmidt (MSE, 2011)

Using dynamic partial reconfiguration to detect sees in microprocessors through non-intrusive hybrid technique. - José Rodrigo Azambuja; Samuel Pagliarini; Maurício Altieri; Fernanda Lima Kastensmidt; Michael Hübner 001; Jürgen Becker 001 (SBCCI, 2011)

Exploring the Limitations of Software-based Techniques in SEE Fault Coverage. - José Rodrigo Azambuja; Samuel Pagliarini; Lucas Rosa; Fernanda Lima Kastensmidt (J. Electron. Test., 2011)

VEasy: a tool suite towards the functional verification challenges. - Samuel Nascimento Pagliarini (2011)

Automatic selective hardening against soft errors: A cost-based and regularity-aware approach. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (ICECS, 2012)

Selective hardening methodology for combinational logic. - Samuel Nascimento Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (LATW, 2012)

Exploring the feasibility of selective hardening for combinational logic. - Samuel N. Pagliarini; G. G. dos Santos; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2012)

Single event transient mitigation through pulse quenching: Effectiveness at circuit level. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (ICECS, 2013)

Reliability assessment of combinational logic using first-order-only fanout reconvergence analysis. - Samuel N. Pagliarini; Tian Ban; Lirida A. B. Naviner; Jean-François Naviner (MWSCAS, 2013)

Selective hardening against multiple faults employing a net-based reliability analysis. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner (NEWCAS, 2013)

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. - Arwa Ben Dhia; Samuel N. Pagliarini; Lirida Alves de Barros Naviner; Habib Mehrez; Philippe Matherat (Microelectron. Reliab., 2013)

SNaP: A novel hybrid method for circuit reliability assessment under multiple faults. - Samuel N. Pagliarini; Arwa Ben Dhia; Lirida Alves de Barros Naviner; Jean-François Naviner (Microelectron. Reliab., 2013)

DeSyRe: On-Demand Adaptive and Reconfigurable Fault-Tolerant SoCs. - Ioannis Sourdis; Christos Strydis; Antonino Armato; Christos-Savvas Bouganis; Babak Falsafi; Georgi Nedeltchev Gaydadjiev; Sebastián Isaza; Alirad Malek; R. Mariani; Samuel N. Pagliarini; Dionisios N. Pnevmatikatos; Dhiraj K. Pradhan; et al. (ARC, 2014)

A hybrid reliability assessment method and its support of sequential logic modelling. - Samuel N. Pagliarini; Lirida A. B. Naviner; Jean-François Naviner; Dhiraj K. Pradhan (IOLTS, 2014)

A placement strategy for reducing the effects of multiple faults in digital circuits. - Samuel N. Pagliarini; Dhiraj K. Pradhan (IOLTS, 2014)

Design and Analysis of Binary Tree Static Random Access Memory for Low Power Embedded Systems. - Luo Sun; Jimson Mathew; Samuel N. Pagliarini; Dhiraj K. Pradhan; Ioannis Sourdis (J. Low Power Electron., 2014)

Evaluating the benefits of relaxed BEOL pitch for deeply scaled ICs. - Mehmet Meric Isgenc; Samuel Pagliarini; Renzhi Liu; Larry T. Pileggi (ISQED, 2017)

Virtual characterization for exhaustive DFM evaluation of logic cell libraries. - Samuel Pagliarini; Mayler G. A. Martins; Lawrence T. Pileggi (ISQED, 2017)

A self-calibrating sense amplifier for a true random number generator using hybrid FinFET-straintronic MTJ. - Sudipta Bhuin; Joseph Sweeney; Samuel Pagliarini; Ayan Kumar Biswas; Lawrence T. Pileggi (NANOARCH, 2017)

A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis. - Rajat Subhra Chakraborty; Samuel Pagliarini; Jimson Mathew; Sree Ranjani Rajendran; M. Nirmala Devi 001 (IEEE Trans. Emerg. Top. Comput., 2017)

Improved Multiple Faults-Aware Placement Strategy: Reducing the Overheads and Error Rates in Digital Circuits. - Mohamad Imran Bin Bandan; Samuel Nascimento Pagliarini; Jimson Mathew; Dhiraj K. Pradhan (IEEE Trans. Reliab., 2017)

An Oscillatory Neural Network with Programmable Resistive Synapses in 28 Nm CMOS. - Thomas C. Jackson; Samuel Pagliarini; Lawrence T. Pileggi (ICRC, 2018)

Application and Product-Volume-Specific Customization of BEOL Metal Pitch. - Samuel N. Pagliarini; Mehmet Meric Isgenc; Mayler G. A. Martins; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Chip-to-Chip Authentication Method Based on SRAM PUF and Public Key Cryptography. - Ioannis Karageorgos; Mehmet Meric Isgenc; Samuel Pagliarini; Lawrence T. Pileggi (J. Hardw. Syst. Secur., 2019)

Latest Trends in Hardware Security and Privacy. - Giorgio Di Natale; Francesco Regazzoni 001; Vincent Albanese; Frank Lhermet; Yann Loisel; Abderrahmane Sensaoui; Samuel Pagliarini (DFT, 2020)

Design Obfuscation versus Test. - Farimah Farahmandi; Ozgur Sinanoglu; Ronald D. Blanton; Samuel Pagliarini (ETS, 2020)

Latch-Based Logic Locking. - Joseph Sweeney; V. Mohammed Zackriya; Samuel Pagliarini; Lawrence T. Pileggi (HOST, 2020)

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges. - Tiago D. Perez; Samuel Pagliarini (IEEE Access, 2020)

Securing Digital Systems via Split-Chip Obfuscation. - Joseph Sweeney; Samuel Pagliarini; Lawrence T. Pileggi (CoRR, 2020)

A Systematic Study of Lattice-based NIST PQC Algorithms: from Reference Implementations to Hardware Accelerators. - Malik Imran; Zain Ul Abideen 002; Samuel Pagliarini (CoRR, 2020)

An Area Aware Accelerator for Elliptic Curve Point Multiplication. - Malik Imran; Samuel Pagliarini; Muhammad Rashid 001 (IACR Cryptol. ePrint Arch., 2020)

From Virtual Characterization to Test-Chips: DFM Analysis Through Pattern Enumeration. - Mayler G. A. Martins; Samuel N. Pagliarini; Mehmet Meric Isgenc; Lawrence T. Pileggi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

A Probabilistic Synapse With Strained MTJs for Spiking Neural Networks. - Samuel N. Pagliarini; Sudipta Bhuin; Mehmet Meric Isgenc; Ayan Kumar Biswas; Lawrence T. Pileggi (IEEE Trans. Neural Networks Learn. Syst., 2020)

Logic IP for Low-Cost IC Design in Advanced CMOS Nodes. - Mehmet Meric Isgenc; Mayler G. A. Martins; V. Mohammed Zackriya; Samuel N. Pagliarini; Lawrence T. Pileggi (IEEE Trans. Very Large Scale Integr. Syst., 2020)

From FPGAs to Obfuscated eASICs: Design and Security Trade-offs. - Zain Ul Abideen 002; Tiago Diadami Perez; Samuel Pagliarini (AsianHOST, 2021)

Side-Channel Attacks on Triple Modular Redundancy Schemes. - Felipe Almeida; Levent Aksoy; Jaan Raik; Samuel Pagliarini (ATS, 2021)

An Open-source Library of Large Integer Polynomial Multipliers. - Malik Imran; Zain Ul Abideen 002; Samuel Pagliarini (DDECS, 2021)

High-level Intellectual Property Obfuscation via Decoy Constants. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IOLTS, 2021)

Side-Channel Trojan Insertion - a Practical Foundry-Side Attack via ECO. - Tiago D. Perez; Malik Imran; Pablo Vaz; Samuel Pagliarini (ISCAS, 2021)

A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization. - Mateus Saquetti; Raphael Martins Brum; Bruno Zatt; Samuel Pagliarini; Weverton Cordeiro; José Rodrigo Azambuja (ISVLSI, 2021)

A Tutorial on Design Obfuscation: from Transistors to Systems. - Samuel Pagliarini (LATS, 2021)

Hardware Trojan Insertion in Finalized Layouts: a Silicon Demonstration. - Tiago D. Perez; Samuel Pagliarini (CoRR, 2021)

Split-Chip Design to Prevent IP Reverse Engineering. - Samuel Pagliarini; Joseph Sweeney; Ken Mai; R. D. Shawn Blanton; Larry T. Pileggi; Subhasish Mitra (IEEE Des. Test, 2021)

Design Space Exploration of SABER in 65nm ASIC. - Malik Imran; Felipe Almeida; Jaan Raik; Andrea Basso 002; Sujoy Sinha Roy; Samuel Pagliarini (IACR Cryptol. ePrint Arch., 2021)

A Side-Channel Hardware Trojan in 65nm CMOS with 2μW precision and Multi-bit Leakage Capability. - Tiago D. Perez; Samuel Pagliarini (ASP-DAC, 2022)

Leveraging Layout-based Effects for Locking Analog ICs. - Muayad J. Aljafar; Florence Azaïs; Marie-Lise Flottes; Samuel Pagliarini (ASHES@CCS, 2022)

G-GPU: A Fully-Automated Generator of GPU-like ASIC Accelerators. - Tiago D. Perez; Marcio M. Gonçalves; Leonardo Gobatto; Marcelo Brandalero; José Rodrigo Azambuja; Samuel Pagliarini (DATE, 2022)

Hardware Obfuscation of Digital FIR Filters. - Levent Aksoy; Alexander Hepp; Johanna Baehr 001; Samuel Pagliarini (DDECS, 2022)

A Pragmatic Methodology for Blind Hardware Trojan Insertion in Finalized Layouts. - Alexander Hepp; Tiago D. Perez; Samuel Pagliarini; Georg Sigl (ICCAD, 2022)

Reusing Verification Assertions as Security Checkers for Hardware Trojan Detection. - Mohammad Eslami; Tara Ghasempouri; Samuel Pagliarini (ISQED, 2022)

Hardware Trojans for Confidence Reduction and Misclassifications on Neural Networks. - Mahdieh Grailoo; Mairo Leier; Samuel Pagliarini (ISQED, 2022)

Obfuscating the Hierarchy of a Digital IP. - Giorgi Basiashvili; Zain Ul Abideen 002; Samuel Pagliarini (SAMOS, 2022)

Ransomware Attack as Hardware Trojan: A Feasibility and Demonstration Study. - Felipe Almeida; Malik Imran; Jaan Raik; Samuel Pagliarini (IEEE Access, 2022)

Preventing Distillation-based Attacks on Neural Network IP. - Mahdieh Grailoo; Zain Ul Abideen 002; Mairo Leier; Samuel Pagliarini (CoRR, 2022)

A Security-aware and LUT-based CAD Flow for the Physical Synthesis of eASICs. - Zain Ul Abideen 002; Tiago Diadami Perez; Mayler G. A. Martins; Samuel Pagliarini (CoRR, 2022)

KaLi: A Crystal for Post-Quantum Security. - Aikata; Ahmet Can Mert; Malik Imran; Samuel Pagliarini; Sujoy Sinha Roy (IACR Cryptol. ePrint Arch., 2022)

Multiplierless Design of Very Large Constant Multiplications in Cryptography. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Patrick Karl; Samuel Pagliarini (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

Benchmarking Advanced Security Closure of Physical Layouts: ISPD 2023 Contest. - Mohammad Eslami; Johann Knechtel; Ozgur Sinanoglu; Ramesh Karri; Samuel Pagliarini (ISPD, 2023)

Resynthesis-based Attacks Against Logic Locking. - Felipe Almeida; Levent Aksoy; Quang-Linh Nguyen; Sophie Dupuis; Marie-Lise Flottes; Samuel Pagliarini (ISQED, 2023)

SALSy: Security-Aware Layout Synthesis. - Mohammad Eslami; Tiago D. Perez; Samuel Pagliarini (CoRR, 2023)

Towards High-speed ASIC Implementations of Post-Quantum Cryptography. - Malik Imran; Aikata; Sujoy Sinha Roy; Samuel N. Pagliarini (IACR Cryptol. ePrint Arch., 2023)

KaLi: A Crystal for Post-Quantum Security Using Kyber and Dilithium. - Aikata; Ahmet Can Mert; Malik Imran; Samuel Pagliarini; Sujoy Sinha Roy (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hybrid Protection of Digital FIR Filters. - Levent Aksoy; Quang-Linh Nguyen; Felipe Almeida; Jaan Raik; Marie-Lise Flottes; Sophie Dupuis; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Hardware Trojan Insertion in Finalized Layouts: From Methodology to a Silicon Demonstration. - Tiago D. Perez; Samuel Pagliarini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Versatile and Flexible Multiplier Generator for Large Integer Polynomials. - Malik Imran; Zain Ul Abideen 002; Samuel Pagliarini (J. Hardw. Syst. Secur., 2023)

A Security-Aware and LUT-Based CAD Flow for the Physical Synthesis of hASICs. - Zain Ul Abideen 002; Tiago Diadami Perez; Mayler G. A. Martins; Samuel Pagliarini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

High-speed SABER key encapsulation mechanism in 65nm CMOS. - Malik Imran; Felipe Almeida; Andrea Basso 002; Sujoy Sinha Roy; Samuel Pagliarini (J. Cryptogr. Eng., 2023)

REPQC: Reverse Engineering and Backdooring Hardware Accelerators for Post-quantum Cryptography. - Samuel Pagliarini; Aikata; Malik Imran; Sujoy Sinha Roy (AsiaCCS, 2024)

Multiplierless Design of High-Speed Very Large Constant Multiplications. - Levent Aksoy; Debapriya Basu Roy; Malik Imran; Samuel Pagliarini (ASPDAC, 2024)

KRATT: QBF-Assisted Removal and Structural Analysis Attack Against Logic Locking. - Levent Aksoy; Muhammad Yasin; Samuel Pagliarini (DATE, 2024)

CAC 2.0: A Corrupt and Correct Logic Locking Technique Resilient to Structural Analysis Attacks. - Levent Aksoy; Muhammad Yasin; Samuel Pagliarini (LATS, 2024)

High-Speed Design of Post Quantum Cryptography With Optimized Hashing and Multiplication. - Malik Imran; Aikata; Sujoy Sinha Roy; Samuel Pagliarini (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Impact of Orientation on the Bias of SRAM-Based PUFs. - Zain Ul Abideen 002; Rui Wang; Tiago Diadami Perez; Geert Jan Schrijen; Samuel Pagliarini (IEEE Des. Test, 2024)

Utilizing layout effects for analog logic locking. - Muayad J. Aljafar; Florence Azaïs; Marie-Lise Flottes; Samuel Pagliarini (J. Cryptogr. Eng., 2024)

An Overview of FPGA-inspired Obfuscation Techniques. - Zain Ul Abideen 002; Sumathi Gokulanathan; Muayad J. Aljafar; Samuel Pagliarini (ACM Comput. Surv., 2024)

SCALLER: Standard Cell Assembled and Local Layout Effect-Based Ring Oscillators. - Muayad J. Aljafar; Zain Ul Abideen 002; Adriaan Peetermans; Benedikt Gierlichs; Samuel Pagliarini (IEEE Embed. Syst. Lett., 2024)

Evaluating NTT/INTT Implementation Styles for Post-Quantum Cryptography. - Malik Imran; Safiullah Khan; Ayesha Khalid; Ciara Rafferty; Yasir Ali Shah; Samuel Pagliarini; Muhammad Rashid 001; Máire O'Neill (IEEE Embed. Syst. Lett., 2024)

SCARF: Securing Chips With a Robust Framework Against Fabrication-Time Hardware Trojans. - Mohammad Eslami; Tara Ghasempouri; Samuel Pagliarini (IEEE Trans. Computers, 2024)

Late Breaking Results: Is Reconfigurable-Based Obfuscation Secure? - Zain Ul Abideen 002; Levent Aksoy; Samuel Pagliarini (DATE, 2025)

Trojan Insertion versus Layout Defenses for Modern ICs: Red-versus-Blue Teaming in a Competitive Community Effort. - Johann Knechtel; Mohammad Eslami; Peng Zou; Min Wei; Xingyu Tong 001; Binggang Qiu; Zhijie Cai; Guohao Chen 001; Benchao Zhu; Jiawei Li; Jun Yu 010; Jianli Chen; et al. (IACR Trans. Cryptogr. Hardw. Embed. Syst., 2025)

RESAA: A Removal and Structural Analysis Attack Against Compound Logic Locking. - Felipe Almeida; Levent Aksoy; Samuel Pagliarini (IEEE Trans. Very Large Scale Integr. Syst., 2025)

A Zero-overhead Flow for Security Closure. - Mohammad Eslami; Ashira Johara; Kyungbin Park; Samuel Pagliarini (CoRR, 2025)