ATUNs: Modular and Scalable Support for Atomic Operations in a Shared Memory Multiprocessor. - Andreas Kurth; Samuel Riedel; Florian Zaruba; Torsten Hoefler; Luca Benini (DAC, 2020)

MemPool: A Shared-L1 Memory Many-Core Cluster with a Low-Latency Interconnect. - Matheus A. Cavalcante; Samuel Riedel; Antonio Pullini; Luca Benini (DATE, 2021)

Banshee: A Fast LLVM-Based RISC-V Binary Translator. - Samuel Riedel; Fabian Schuiki; Paul Scheffler; Florian Zaruba; Luca Benini (ICCAD, 2021)

MemPool-3D: Boosting Performance and Efficiency of Shared-L1 Memory Many-Core Clusters with 3D Integration. - Matheus A. Cavalcante; Anthony Agnesina; Samuel Riedel; Moritz Brunion; Alberto García-Ortiz; Dragomir Milojevic; Francky Catthoor; Sung Kyu Lim; Luca Benini (DATE, 2022)

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters. - Matheus A. Cavalcante; Domenic Wüthrich; Matteo Perotti; Samuel Riedel; Luca Benini (ICCAD, 2022)

Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. - Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (ISLPED, 2022)

MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor Cluster. - Samuel Riedel; Gua Hao Khov; Sergio Mazzola; Matheus A. Cavalcante; Renzo Andri; Luca Benini (DATE, 2023)

MinPool: A 16-core NUMA-L1 Memory RISC-V Processor Cluster for Always-on Image Processing in 65nm CMOS. - Samuel Riedel; Matheus A. Cavalcante; Manos Frouzakis; Domenic Wüthrich; Enis Mustafa; Arlind Billa; Luca Benini (ICECS, 2023)

Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster. - Marco Bertuletti; Samuel Riedel; Yichao Zhang 003; Alessandro Vanelli-Coralli; Luca Benini (SAMOS, 2023)

MemPool: A Scalable Manycore Architecture With a Low-Latency Shared L1 Memory. - Samuel Riedel; Matheus A. Cavalcante; Renzo Andri; Luca Benini (IEEE Trans. Computers, 2023)

LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation. - Samuel Riedel; Marc Gantenbein; Alessandro Ottaviano; Torsten Hoefler; Luca Benini (DATE, 2024)

TeraPool-SDR: An 1.89TOPS 1024 RV-Cores 4MiB Shared-L1 Cluster for Next-Generation Open-Source Software-Defined Radios. - Yichao Zhang 003; Marco Bertuletti; Samuel Riedel; Matheus A. Cavalcante; Alessandro Vanelli-Coralli; Luca Benini (ACM Great Lakes Symposium on VLSI, 2024)

3D Partitioning with Pipeline Optimization for Low-Latency Memory Access in Many-Core SoCs. - Sudipta Das; Samuel Riedel; Marco Bertuletti; Luca Benini; Moritz Brunion; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (ISCAS, 2024)

A 1024 RV-Cores Shared-L1 Cluster with High Bandwidth Memory Link for Low-Latency 6G-SDR. - Yichao Zhang 003; Marco Bertuletti; Chi Zhang; Samuel Riedel; Alessandro Vanelli-Coralli; Luca Benini (CoRR, 2024)

A High-Performance, Energy-Efficient Modular DMA Engine Architecture. - Thomas Benz; Michael Rogenmoser; Paul Scheffler; Samuel Riedel; Alessandro Ottaviano; Andreas Kurth; Torsten Hoefler; Luca Benini (IEEE Trans. Computers, 2024)

Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. - Nesara Eranna Bethur; Anthony Agnesina; Moritz Brunion; Alberto García Ortiz; Francky Catthoor; Dragomir Milojevic; Manu Komalan; Matheus A. Cavalcante; Samuel Riedel; Luca Benini; Sung Kyu Lim (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Enabling Efficient Hybrid Systolic Computation in Shared-L1-Memory Manycore Clusters. - Sergio Mazzola; Samuel Riedel; Luca Benini (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Optimizing Scalable Multi-Cluster Architectures for Next-Generation Wireless Sensing and Communication. - Samuel Riedel; Yichao Zhang 003; Marco Bertuletti; Luca Benini (IWASI, 2025)

Bandwidth-Latency-Thermal Co-Optimization of Interconnect-Dominated Many-Core 3D-IC. - Sudipta Das; Samuel Riedel; Mohamed Naeim; Moritz Brunion; Marco Bertuletti; Luca Benini; Julien Ryckaert; James Myers; Dwaipayan Biswas; Dragomir Milojevic (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Area Comparison of CHERIoT and PMP in Ibex. - Samuel Riedel; Marno van der Maas; John Thomson; Andreas Kurth; Pirmin Vogel (CoRR, 2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency. - Matteo Perotti; Samuel Riedel; Matheus A. Cavalcante; Luca Benini (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)