MIST: monitor generation from informal specifications for firmware verification. - Samuele Germiniani; Moreno Bragaglio; Graziano Pravadelli (VLSI-SOC, 2020)

From Informal Specifications to an ABV Framework for Industrial Firmware Verification. - Samuele Germiniani; Moreno Bragaglio; Graziano Pravadelli (VLSI-SoC (Selected Papers), 2020)

A containerized ROS-compliant verification environment for robotic systems. - Stefano Aldegheri; Nicola Bombieri; Samuele Germiniani; Federico Moschin; Graziano Pravadelli (DATE, 2021)

System-level bug explanation through program slicing and instruction clusterization. - Moreno Bragaglio; Nicola Donatelli; Samuele Germiniani; Graziano Pravadelli (VLSI-SoC, 2021)

Exploiting Program Slicing and Instruction Clusterization to Identify the Cause of Faulty Temporal Behaviours at System Level. - Moreno Bragaglio; Samuele Germiniani; Graziano Pravadelli (VLSI-SoC (Selected Papers), 2021)

Risk Assessment and Prediction in Human-Robot Interaction Through Assertion Mining and Pose Estimation. - Michele Boldo; Nicola Bombieri; Mirco De Marchi; Luca Geretti; Samuele Germiniani; Graziano Pravadelli (LATS, 2022)

Assertion-aware approximate computing design exploration on behavioral models. - Alberto Bosio; Moreno Bragaglio; Samuele Germiniani; Samuele Mori; Graziano Pravadelli; Marcello Traiola (LATS, 2022)

Exploiting clustering and decision-tree algorithms to mine LTL assertions containing non-boolean expressions. - Samuele Germiniani; Graziano Pravadelli (VLSI-SoC, 2022)

HARM: A Hint-Based Assertion Miner. - Samuele Germiniani; Graziano Pravadelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Automatic Generation of Assertions for Detection of Firmware Vulnerabilities Through Alignment of Symbolic Sequences. - Samuele Germiniani; Alessandro Danese; Graziano Pravadelli (IEEE Trans. Emerg. Top. Comput., 2022)

Exploiting assertions mining and fault analysis to guide RTL-level approximation. - Alberto Bosio; Samuele Germiniani; Graziano Pravadelli; Marcello Traiola (DATE, 2023)

Mining signal temporal logic specifications for hybrid systems. - Daniele Nicoletti; Samuele Germiniani; Graziano Pravadelli (FDL, 2024)

Invited Talk: Pros and Cons of Assertion Mining. - Samuele Germiniani; Daniele Nicoletti; Graziano Pravadelli (LATS, 2024)

Enhancing Safety and Privacy in Industry 4.0: The ICE Laboratory Case Study. - Federico Cunico; Stefano Aldegheri; Andrea Avogaro; Michele Boldo; Nicola Bombieri; Luigi Capogrosso; Ariel Caputo; Damiano Carra; Stefano Centomo; Dong Seon Cheng; Ettore Cinquetti; Marco Cristani; et al. (IEEE Access, 2024)

Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs. - Alberto Bosio; Samuele Germiniani; Graziano Pravadelli; Marcello Traiola (J. Electron. Test., 2024)

A Baseline Framework for the Qualification of LTL Specification Miners. - Samuele Germiniani; Daniele Nicoletti; Graziano Pravadelli (DATE, 2025)

Special Session: A Model-Driven Design Tool for Modelling, Simulation and Assertion-Based Verification of Hybrid Automata. - Daniele Nicoletti; Samuele Germiniani; Alessandro Aldegheri; Michele Cipriani; Davide Venturi; Tommaso Vilotto; Graziano Pravadelli (LATS, 2025)

A Systematic Literature Review on Mining LTL Specifications. - Samuele Germiniani; Daniele Nicoletti; Graziano Pravadelli (IEEE Access, 2025)