Automatic Code-Transformation and Architecture Refinement for Application-Specific Multiprocessor SoCs with Shared Memory. - Samy Meftali; Ferid Gharsalli; Frédéric Rousseau 001; Ahmed Amine Jerraya (VLSI-SOC, 2001)

An optimal memory allocation for application-specific multiprocessor system-on-chip. - Samy Meftali; Ferid Gharsalli; Frédéric Rousseau 001; Ahmed Amine Jerraya (ISSS, 2001)

Automatic generation of embedded memory wrapper for multiprocessor SoC. - Ferid Gharsalli; Samy Meftali; Frédéric Rousseau 001; Ahmed Amine Jerraya (DAC, 2002)

Unifying Memory and Processor Wrapper Architecture in Multiprocessor SoC Design. - Ahmed Amine Jerraya; Damien Lyonnard; Samy Meftali; Frédéric Rousseau 001; Ferid Gharsalli (ISSS, 2002)

Exploration d'architectures et allocation/affectation mémoire dans les systèmes multiprocesseurs mono puce = Architectures exploration and memory allocation/assignment in multiprocessor SoC. (Architectures exploration and memory allocation/assignment in multiprocessor SoC). - Samy Meftali (2002)

MDA Based, SystemC Code Generation, Applied to Intensive Signal Processing Applications. - M. Samyn; Samy Meftali; Jean-Luc Dekeyser (FDL, 2004)

An automatic communication synthesis for high level SOC desing using transaction level modelling (poster). - E. Turbatu; Samy Meftali; Smaïl Niar; Jean-Luc Dekeyser (FDL, 2004)

SoCP2P: A Peer-to-Peer IPS Based SoC Design and Simulation Tool. - Samy Meftali; Jean-Luc Dekeyser (Virtual Enterprises and Collaborative Networks, 2004)

An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. - Samy Meftali; Jean-Luc Dekeyser (IWSOC, 2004)

SOAP Based Distributed Simulation Environment for SoC Design. - Samy Meftali; Anouar Dziri; Luc Charest; Philippe Marquet; J. Deskeyser (FDL, 2005)

Embed Scripting inside SystemC. - J. Vennin; S. Penain; Luc Charest; Samy Meftali; Jean-Luc Dekeyser (FDL, 2005)

Scalable Multistage Network for Multiprocessor System-on-Chip Design. - Samy Meftali; Jean-Luc Dekeyser; Isaac D. Scherson (ISPAN, 2005)

Estimating Energy Consumption for an MPSoC Architectural Exploration. - Rabie Ben Atitallah; Smaïl Niar; Alain Greiner; Samy Meftali; Jean-Luc Dekeyser (ARCS, 2006)

Multilevel MPSoC Performance Evaluation Using MDE Approach. - Rabie Ben Atitallah; Lossan Bonde; Smaïl Niar; Samy Meftali; Jean-Luc Dekeyser (SoC, 2006)

Massively parallel processing on a chip. - Philippe Marquet; Simon Duquennoy; Sébastien Le Beux; Samy Meftali; Jean-Luc Dekeyser (Conf. Computing Frontiers, 2007)

An MPSoC Performance Estimation Framework Using Transaction Level Modeling. - Rabie Ben Atitallah; Smaïl Niar; Samy Meftali; Jean-Luc Dekeyser (RTCSA, 2007)

MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (ESTIMedia, 2008)

Using an MDE Approach for Modeling of Interconnection Networks. - Imran Rafiq Quadri; Pierre Boulet; Samy Meftali; Jean-Luc Dekeyser (ISPAN, 2008)

High level modeling of Dynamic Reconfigurable FPGAs. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (Int. J. Reconfigurable Comput., 2009)

Vers la reconfiguration dynamique dans les systèmes embarqués: de la modélisation à l'implémentation. (Toward Dynamically Reconfigurable in Embedded Systems: From Models to Implementations). - Samy Meftali (2010)

Designing dynamically reconfigurable SoCs: From UML MARTE models to automatic code generation. - Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2010)

Modeling Reconfigurable Systems-on-Chips with UML MARTE Profile: An Exploratory Analysis. - Sana Cherif; Imran Rafiq Quadri; Samy Meftali; Jean-Luc Dekeyser (DSD, 2010)

A Low power and highly parallel implementation of the H.264 8 × 8 transform and quantization. - Majdi Elhaji; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (ISSPIT, 2010)

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation. - Imran Rafiq Quadri; Huafeng Yu; Abdoulaye Gamatié; Éric Rutten; Samy Meftali; Jean-Luc Dekeyser (Int. J. Embed. Syst., 2010)

High level design of adaptive distributed controller for partial dynamic reconfiguration in FPGA. - Sana Cherif; Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2011)

FeRoNoC: Flexible and extensible Router implementation for diagonal mesh topology. - Majdi Elhaji; Brahim Attia; Abdelkrim Zitouni; Rached Tourki; Samy Meftali; Jean-Luc Dekeyser (DASIP, 2011)

A Model-Driven Approach for Hybrid Power Estimation in Embedded Systems Design. - Chiraz Trabelsi; Rabie Ben Atitallah; Samy Meftali; Jean-Luc Dekeyser; Abderrazek Jemai (EURASIP J. Embed. Syst., 2011)

Semi-distributed Control for FPGA-based Reconfigurable Systems. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (DSD, 2012)

Facilitating IP deployment in a MARTE-based MDE methodology using IP-XACT: A Xilinx EDK case study. - Gilberto Ochoa-Ruiz; Ouassila Labbani-Narsis; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (ReConFig, 2012)

Distributed control for reconfigurable FPGA systems: A high-level design approach. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (ReCoSoC, 2012)

Enabling partially reconfigurable IP cores parameterisation and integration using MARTE and IP-XACT. - Gilberto Ochoa-Ruiz; Ouassila Labbani; El-Bay Bourennane; Sana Cherif; Samy Meftali; Jean-Luc Dekeyser (RSP, 2012)

System level modeling methodology of NoC design from UML-MARTE to VHDL. - Majdi Elhaji; Pierre Boulet; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (Des. Autom. Embed. Syst., 2012)

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives. - Imran Rafiq Quadri; Abdoulaye Gamatié; Pierre Boulet; Samy Meftali; Jean-Luc Dekeyser (J. Syst. Archit., 2012)

A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme. - Majdi Elhaji; Abdelkrim Zitouni; Samy Meftali; Jean-Luc Dekeyser; Rached Tourki (Integr., 2013)

Decentralized control for dynamically reconfigurable FPGA systems. - Chiraz Trabelsi; Samy Meftali; Jean-Luc Dekeyser (Microprocess. Microsystems, 2013)

Model-driven design flow for distributed control in reconfigurable FPGA systems. - Chiraz Trabelsi; Samy Meftali; Rabie Ben Atitallah; Jean-Luc Dekeyser (DASIP, 2014)

A Survey of Keylogger and Screenlogger Attacks in the Banking Sector and Countermeasures to Them. - Hugo Sbai; Michael Goldsmith; Samy Meftali; Jassim Happa (CSS, 2018)

A modeling front-end for seamless design and generation of context-aware Dynamically Reconfigurable Systems-on-Chip. - Gilberto Ochoa-Ruiz; Pamela Wattebled; Maamar Touiza; Florent de Lamotte; El-Bay Bourennane; Samy Meftali; Jean-Luc Dekeyser; Jean-Philippe Diguet (J. Parallel Distributed Comput., 2018)

An Optimal Allocation of Tracking Tasks in a SW/HW Fog/Cloud Based Distributed Video Surveillance System. - Ugo Sbai; Samy Meftali; Djamel Aouali (J. Commun., 2019)

Dataset Construction and Analysis of Screenshot Malware. - Hugo Sbaï; Jassim Happa; Michael Goldsmith; Samy Meftali (TrustCom, 2020)

A survey on screenlogger attacks as well as countermeasures. - Hugo Sbai; Jassim Happa; Michael Goldsmith; Samy Meftali (Int. J. Embed. Syst., 2020)

Gene selection and classification of microarray data method based on mutual information and moth flame algorithm. - Ali Dabba; Abdelkamel Tari; Samy Meftali; Rabah Mokhtari (Expert Syst. Appl., 2021)

Hybridization of Moth flame optimization algorithm and quantum computing for gene selection in microarray data. - Ali Dabba; Abdelkamel Tari; Samy Meftali (J. Ambient Intell. Humaniz. Comput., 2021)

A new multi-objective binary Harris Hawks optimization for gene selection in microarray data. - Ali Dabba; Abdelkamel Tari; Samy Meftali (J. Ambient Intell. Humaniz. Comput., 2023)

A novel grey wolf optimization algorithm based on geometric transformations for gene selection and cancer classification. - Ali Dabba; Abdelkamel Tari; Samy Meftali (J. Supercomput., 2024)

ModNEF : An Open Source Modular Neuromorphic Emulator for FPGA for Low-Power In-Edge Artificial Intelligence. - Aurélie Saulquin; Mazdak Fatahi; Pierre Boulet; Samy Meftali (ACM Trans. Archit. Code Optim., 2025)