Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (ASAP, 2018)

Scalable High Performance SDN Switch Architecture on FPGA for Core Networks. - Sasindu Wijeratne; Ashen Ekanayake; Sandaruwan Jayaweera; Danuka Ravishan; Ajith Pasqual (FPGA, 2019)

Co-Existence of ITS-G5 and C-V2X at an Urban Road Intersection. - Sandaruwan Jayaweera; K. B. Shashika Manosha; Nandana Rajatheva; Matti Latva-aho (EuCNC/6G Summit, 2021)

Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks. - Sasindu Wijeratne; Sandaruwan Jayaweera; Mahesh Dananjaya; Ajith Pasqual (CoRR, 2021)

Enabling Cooperative Awareness for UAVs: ETSI CAM Protocol Extension. - Sandaruwan Jayaweera; Konstantin Mikhaylov; Matti Hämäläinen (EuCNC, 2022)

Enabling Cooperative Awareness for Miniature UAVs with BLE5: Range Analysis and Experimental Measurement. - Sandaruwan Jayaweera; Konstantin Mikhaylov; Matti Hämäläinen (WF-IoT, 2023)

BLE-Based Cooperative Awareness for Miniature UAVs: Simulation and Experimental Analysis. - Sandaruwan Jayaweera; Konstantin Mikhaylov; Matti Hämäläinen (IEEE Internet Things J., 2025)