Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures. - Hui Wang; Sandeep Baldawa; Rama Sangireddy (VLSI Design, 2008)

Optimizing Instruction Scheduling through Combined In-Order and O-O-O Execution in SMT Processors. - Hui Wang; Rama Sangireddy; Sandeep Baldawa (IEEE Trans. Parallel Distributed Syst., 2009)