Heuristic random optimizer-version II. - Sandeep Chandran; R. Russell Rhinehart (ACC, 2002)

Space sensitive cache dumping for post-silicon validation. - Sandeep Chandran; Smruti R. Sarangi; Preeti Ranjan Panda (DATE, 2013)

Architectural Support for Handling Jitterin Shared Memory Based Parallel Applications. - Sandeep Chandran; Prathmesh Kallurkar; Parul Gupta; Smruti R. Sarangi (IEEE Trans. Parallel Distributed Syst., 2014)

Fundamental Results for a Generic Implementation of Barriers using Optical Interconnects. - Sandeep Chandran; Eldhose Peter; Preeti Ranjan Panda; Smruti R. Sarangi (CoRR, 2015)

Extending trace history through tapered summaries in post-silicon validation. - Sandeep Chandran; Preeti Ranjan Panda; Deepak Chauhan; Sharad Kumar; Smruti R. Sarangi (ASP-DAC, 2016)

A Generic Implementation of Barriers Using Optical Interconnects. - Sandeep Chandran; Eldhose Peter; Preeti Ranjan Panda; Smruti R. Sarangi (VLSID, 2016)

Area-Aware Cache Update Trackers for Postsilicon Validation. - Sandeep Chandran; Smruti R. Sarangi; Preeti Ranjan Panda (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Managing Trace Summaries to Minimize Stalls During Postsilicon Validation. - Sandeep Chandran; Preeti Ranjan Panda; Smruti R. Sarangi; Ayan Bhattacharyya; Deepak Chauhan; Sharad Kumar (IEEE Trans. Very Large Scale Integr. Syst., 2017)

DHOOM: Reusing Design-for-Debug Hardware for Online Monitoring. - Neetu Jindal; Sandeep Chandran; Preeti Ranjan Panda; Sanjiva Prasad; Abhay Mitra; Kunal Singhal; Shubham Gupta; Shikhar Tuli (DAC, 2019)

SANNA: Secure Acceleration of Neural Network Applications. - Akash Poptani; Abhishek Mittal; Rishit Saiya; Rajshekar Kalayappan; Sandeep Chandran (VLSID, 2023)

Dynamic Ineffectuality-based Clustered Architectures. - Rajshekar Kalayappan; Sandeep Chandran (CoRR, 2023)

On Decomposing Complex Test Cases for Efficient Post-silicon Validation. - C. Harshitha; Sundarapalli Harikrishna; Peddakotla Rohith; Sandeep Chandran; Rajshekar Kalayappan (ASPDAC, 2024)

CASH: Criticality-Aware Split Hybrid L1 Data Cache. - Shruthi Karunakar; Meenakshi Atkade; Akash Poptani; Rajshekar Kalayappan; Sandeep Chandran (ACM Great Lakes Symposium on VLSI, 2024)

faRM-LTL: A Domain-Specific Architecture for Flexible and Accelerated Runtime Monitoring of LTL Properties. - Amrutha Benny; Sandeep Chandran; Rajshekar Kalayappan; Ramchandra Phawade; Piyush P. Kurur (RV, 2024)

Consequence-based Clustered Architecture. - Shruthi Karunakar; Rajshekar Kalayappan; Sandeep Chandran (ACM Trans. Archit. Code Optim., 2025)