Design and Analysis of Power and Area Efficient Novel Concurrent Cellular Automation Logic Block Observer BIST Structure. - Sandeep Dhariwal; Ravi Trivedi (Int. J. Perform. Eng., 2020)

Delay Reduction by Implementation of Voltage-Controlled Ring Oscillator with Reverse Substrate Bias. - Ravi Shankar Mishra; Sandeep Dhariwal (Int. J. Perform. Eng., 2020)

Hybrid GDI PTL Full Adder: A Proposed Design for Low Power Applications. - Sandeep Dhariwal; Reeba Korah; Ravi Shankar Mishra; Gaurav Kumar (Int. J. Perform. Eng., 2022)

Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach. - Anubhav Anand; Satyam Singh 005; Sandeep Dhariwal; Reeba Korah; Gaurav Kumar (Int. J. Perform. Eng., 2023)