Concurrent Control of Multiple BIT Structures. - Sandeep K. Gupta 001; Melvin A. Breuer; Jung-Cheun Lien (ITC, 1988)

A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing Probability. - Sandeep K. Gupta 001; Dhiraj K. Pradhan (ITC, 1988)

Zero aliasing compression. - Sandeep K. Gupta 001; Dhiraj K. Pradhan; Sudhakar M. Reddy (FTCS, 1990)

Aliasing Probability for Multiple Input Signature Analyzer. - Dhiraj K. Pradhan; Sandeep K. Gupta 001; Mark G. Karpovsky (IEEE Trans. Computers, 1990)

Aliasing and Diagnosis Probability in MISR and STUMPS Using a General Error Model. - Mark G. Karpovsky; Sandeep K. Gupta 001; Dhiraj K. Pradhan (ITC, 1991)

A New Framework for Designing and Analyzing BIST Techniques and Zero Aliasing Compression. - Dhiraj K. Pradhan; Sandeep K. Gupta 001 (IEEE Trans. Computers, 1991)

Can Concurrent Checkers Help BIST? - Sandeep K. Gupta 001; Dhiraj K. Pradhan (ITC, 1992)

Recent advances in BIST. - Sandeep K. Gupta 001 (VTS, 1992)

An Efficient Partitioning Strategy for Pseudo-Exhaustive Testing. - Rajagopalan Srinivasan; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1993)

Novel Test Pattern Generators for Pseudo-Exhaustive Testing. - Rajagopalan Srinivasan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 1993)

Clock Grouping: A Low Cost DFT Methodology for Delay Testing. - Wen-Chang Fang; Sandeep K. Gupta 001 (DAC, 1994)

BIST Test Pattern Generators for Stuck-Open and Delay Testing. - Chih-Ang Chen; Sandeep K. Gupta 001 (EDAC-ETC-EUROASIC, 1994)

A Low Cost BIST Methodology and Associated Novel Test Pattern Generator. - Sen-Pin Lin; Sandeep K. Gupta 001; Melvin A. Breuer (EDAC-ETC-EUROASIC, 1994)

Random pattern testable logic synthesis. - Chen-Huan Chiang; Sandeep K. Gupta 001 (ICCAD, 1994)

A comprehensive fault macromodel for opamps. - Chen-Yang Pan; Kwang-Ting Cheng; Sandeep Gupta 001 (ICCAD, 1994)

Weighted random robust path delay testing of synthesized multilevel circuits. - Weili Wang; Sandeep K. Gupta 001 (VTS, 1994)

Data Path Allocation for Synthesizing RTL Designs with Low BIST Area Overhead. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1995)

Test embedding with discrete logarithms. - Mody Lempel; Sandeep K. Gupta 001; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995)

A Satisfiability-Based Test Generator for Path Delay Faults in Combinational Circuts. - Chih-Ang Chen; Sandeep K. Gupta 001 (DAC, 1996)

Lower Bounds on Test Resources for Scheduled Data Flow Graphs. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1996)

Process-Aggravated Noise (PAN): New Validation and Test Problems. - Melvin A. Breuer; Sandeep K. Gupta 001 (ITC, 1996)

Delay Fault Testing: How Robust are Our Models? - Sandeep K. Gupta 001; Slawomir Pilarski; Sudhakar M. Reddy; Jacob Savir; Prab Varma (VTS, 1996)

Fault macromodeling and a testing strategy for opamps. - Chen-Yang Pan; Kwang-Ting Cheng; Sandeep Gupta 001 (J. Electron. Test., 1996)

BIST Test Pattern Generators for Two-Pattern Testing-Theory and Design Algorithms. - Chih-Ang Chen; Sandeep K. Gupta 001 (IEEE Trans. Computers, 1996)

Utilization of On-Line (Concurrent) Checkers During Built-In-Self-Test and Vice Versa. - Sandeep K. Gupta 001; Dhiraj K. Pradhan (IEEE Trans. Computers, 1996)

A Simulator for At-Speed Robust Testing of Path Delay Faults in Combinational Circuits. - Yuan-Chieh Hsu; Sandeep K. Gupta 001 (IEEE Trans. Computers, 1996)

ATPG for Heat Dissipation Minimization During Scan Testing. - Seongmoon Wang; Sandeep K. Gupta 001 (DAC, 1997)

BIST TPG for faults in system backplanes. - Chen-Huan Chiang; Sandeep K. Gupta 001 (ICCAD, 1997)

Analytic Models for Crosstalk Delay and Pulse Analysis Under Non-Ideal Inputs. - Weiyu Chen; Melvin A. Breuer; Sandeep K. Gupta 001 (ITC, 1997)

DS-LFSR: A New BIST TPG for Low Heat Dissipation. - Seongmoon Wang; Sandeep K. Gupta 001 (ITC, 1997)

Analysis of Ground Bounce in Deep Sub-Micron Circuits. - Yi-Shing Chang; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 1997)

High Quality Robust Tests for Path Delay Faults. - Liang-Chi Chen; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 1997)

BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. - Chen-Huan Chiang; Sandeep K. Gupta 001 (VTS, 1997)

BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (Asian Test Symposium, 1998)

An Automatic Test Pattern Generator for At-Speed Robust Path Delay Testing. - Yuan-Chieh Hsu; Sandeep K. Gupta 001 (Asian Test Symposium, 1998)

Introducing Redundant Computations in a Behavior for Reducing BIST Resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 1998)

Scheduling and Module Assignment for Reducing Bist Resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (DATE, 1998)

Process Variations and their Impact on Circuit Operation. - Suriyaprakash Natarajan; Melvin A. Breuer; Sandeep K. Gupta 001 (DFT, 1998)

Fault-oriented Test Generation for Multicast Routing Protocol Design. - Ahmed Helmy; Deborah Estrin; Sandeep Gupta 001 (FORTE, 1998)

Test generation in VLSI circuits for crosstalk noise. - Weiyu Chen; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 1998)

A new path-oriented effect-cause methodology to diagnose delay failures. - Yuan-Chieh Hsu; Sandeep K. Gupta 001 (ITC, 1998)

A Methodology for Transforming Memory Tests for In-System Testing of Direct Mapped Cache Tags. - Sultan M. Al-Harbi; Sandeep K. Gupta 001 (VTS, 1998)

Allocation Techniques for Reducing BIST Area Overhead of Data Paths. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 1998)

Estimation of BIST Resources During High-Level Synthesis. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 1998)

ATPG for Heat Dissipation Minimization During Test Application. - Seongmoon Wang; Sandeep K. Gupta 001 (IEEE Trans. Computers, 1998)

Bounds on pseudoexhaustive test lengths. - Rajagopalan Srinivasan; Sandeep K. Gupta 001; Melvin A. Breuer (IEEE Trans. Very Large Scale Integr. Syst., 1998)

Validation and test generation for oscillatory noise in VLSI interconnects. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (ICCAD, 1999)

Test generation for crosstalk-induced delay in integrated circuits. - Wei-Yu Chen; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 1999)

Switch-level delay test. - Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 1999)

LT-RTPG: a new test-per-scan BIST TPG for low heat dissipation. - Seongmoon Wang; Sandeep K. Gupta 001 (ITC, 1999)

Test Generation for Ground Bounce in Internal Logic Circuitry. - Yi-Shing Chang; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 1999)

A new framework for static timing analysis, incremental timing refinement, and timing simulation. - Liang-Chi Chen; Sandeep K. Gupta 001; Melvin A. Breuer (Asian Test Symposium, 2000)

Test generation for crosstalk-induced faults: framework and computational result. - Wei-Yu Chen; Sandeep K. Gupta 001; Melvin A. Breuer (Asian Test Symposium, 2000)

BIST TPG for SRAM cluster interconnect testing at board level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (Asian Test Symposium, 2000)

Systematic Performance Evaluation of Multipoint Protocols. - Ahmed Helmy; Sandeep Gupta 001; Deborah Estrin; Alberto Cerpa; Yan Yu (FORTE, 2000)

Systematic testing of multicast routing protocols: analysis of forward and backward search techniques. - Ahmed Helmy; Deborah Estrin; Sandeep Gupta 001 (ICCCN, 2000)

Test generation for path-delay faults in one-dimensional iterative logic arrays. - Nabil M. Abdulrazzaq; Sandeep K. Gupta 001 (ITC, 2000)

Systematic Testing of Protocol Robustness: Case Studies on Mobile IP and MARS. - Shamim Begum; Meeta Sharma; Ahmed Helmy; Sandeep Gupta 001 (LCN, 2000)

New Validation and Test Problems for High Performance Deep Submicron VLSI Circuits. - Melvin A. Breuer; Sandeep K. Gupta 001 (VLSI Design, 2000)

A Framework to Minimize Test Escape and Yield Loss during IDDQ Testing: A Case Study. - Hugo Cheung; Sandeep K. Gupta 001 (VTS, 2000)

BIST TPG for Combinational Cluster Interconnect Testing at Board Level. - Chen-Huan Chiang; Sandeep K. Gupta 001 (J. Electron. Test., 2000)

Novel Test Pattern Generators for Pseudoexhaustive Testing. - Rajagopalan Srinivasan; Sandeep K. Gupta 001; Melvin A. Breuer (IEEE Trans. Computers, 2000)

A New Gate Delay Model for Simultaneous Switching and Its Applications. - Liang-Chi Chen; Sandeep K. Gupta 001; Melvin A. Breuer (DAC, 2001)

Exact fault simulation for systems on Silicon that protects each core's intellectual property. - Md. Saffat Quasem; Sandeep K. Gupta 001 (DATE, 2001)

Crosstalk test generation on pseudo industrial circuits: a case study. - Liang-Chi Chen; T. M. Mak; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2001)

Switch-level delay test of domino logic circuits. - Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2001)

An Efficient Methodology for Generating Optimal and Uniform March Tests. - Sultan M. Al-Harbi; Sandeep K. Gupta 001 (VTS, 2001)

Test Generation for Maximizing Ground Bounce for Internal Circuitry with Reconvergent Fan-out. - Yi-Shing Chang; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 2001)

Path delay fault diagnosis in combinational circuits with implicitfault enumeration. - Pankaj Pant; Yuan-Chieh Hsu; Sandeep K. Gupta 001; Abhijit Chatterjee (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001)

Introducing redundant computations in RTL data paths for reducing BIST resources. - Ishwar Parulkar; Sandeep K. Gupta 001; Melvin A. Breuer (ACM Trans. Design Autom. Electr. Syst., 2001)

Enhanced Crosstalk Fault Model and Methodology to Generate Tests for Arbitrary Inter-core Interconnect Topology. - Wichian Sirisaengtaksin; Sandeep K. Gupta 001 (Asian Test Symposium, 2002)

Accurate and Efficient Static Timing Analysis with Crosstalk. - I-De Huang; Sandeep K. Gupta 001; Melvin A. Breuer (ICCD, 2002)

An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes. - Zhigang Jiang; Sandeep K. Gupta 001 (ITC, 2002)

XIDEN: Crosstalk Target Identification Framework. - Shahin Nazarian; Hang Huang; Suriyaprakash Natarajan; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2002)

Test Generation for Crosstalk-Induced Faults: Framework and Computational Results. - Wei-Yu Chen; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 2002)

TA-PSV - Timing Analysis for Partially Specified Vectors. - Liang-Chi Chen; Sandeep K. Gupta 001; Melvin A. Breuer (J. Electron. Test., 2002)

Analytical models for crosstalk excitation and propagation in VLSI circuits. - Wei-Yu Chen; Sandeep K. Gupta 001; Melvin A. Breuer (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

DS-LFSR: a BIST TPG for low switching activity. - Seongmoon Wang; Sandeep K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An automatic test pattern generator for minimizing switching activity during scan testing activity. - Seongmoon Wang; Sandeep K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002)

An Efficient PIM (Processor-In-Memory) Architecture for Motion Estimation. - Jung-Yup Kang; Sandeep Gupta 001; Saurabh Shah; Jean-Luc Gaudiot (ASAP, 2003)

A Test Generation Approach for Systems-on-Chip that Use Intellectual Property Cores. - Zhigang Jiang; Sandeep K. Gupta 001 (Asian Test Symposium, 2003)

Designing Multiple Scan Chains for Systems-on-Chip. - Md. Saffat Quasem; Sandeep K. Gupta 001 (Asian Test Symposium, 2003)

An Enhanced Test Generator for Capacitance Induced Crosstalk Delay Faults. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (Asian Test Symposium, 2003)

Structural Delay Testing of Latch-based High-speed Pipelines with Time Borrowing. - Kun Young Chung; Sandeep K. Gupta 001 (ITC, 2003)

Path-Delay Fault Simulation for Circuits with Large Numbers of Paths for Very Large Test Sets. - Nabil M. Abdulrazzaq; Sandeep K. Gupta 001 (VTS, 2003)

Generating Complete and Optimal March Tests for Linked Faults in Memories. - Sultan M. Al-Harbi; Sandeep K. Gupta 001 (VTS, 2003)

Test Generation for Maximizing Ground Bounce Considering Circuit Delay. - Yi-Shing Chang; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 2003)

Analyzing Crosstalk in the Presence of Weak Bridge Defects. - Shahdad Irajpour; Shahin Nazarian; Lei Wang; Sandeep K. Gupta 001; Melvin A. Breuer (VTS, 2003)

Benefits of a SoC-Specific Test Methodology. - Md. Saffat Quasem; Zhigang Jiang; Sandeep K. Gupta 001 (IEEE Des. Test Comput., 2003)

Efficient Identification of Crosstalk Induced Slowdown Targets. - Melvin A. Breuer; Sandeep K. Gupta 001; Shahin Nazarian (Asian Test Symposium, 2004)

Modeling and Testing Crosstalk Faults in Inter-Core Interconnects that Include Tri-State and Bi-Directional Nets. - Wichian Sirisaengtaksin; Sandeep K. Gupta 001 (Asian Test Symposium, 2004)

Modeling and Simulation for Crosstalk Aggravated by Weak-Bridge Defects between On-Chip Interconnects. - Lei Wang; Sandeep K. Gupta 001; Melvin A. Breuer (Asian Test Symposium, 2004)

Accelerating the Kernels of BLAST with an Efficient PIM (Processor-In-Memory) Architecture. - Jung-Yup Kang; Sandeep Gupta 001; Jean-Luc Gaudiot (CSB, 2004)

Timing-Independent Testing of Crosstalk in the Presence of Delay Producing Defects Using Surrogate Fault Models. - Shahdad Irajpour; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2004)

Designing Reconfigurable Multiple Scan Chains for Systems-on-Chip. - Md. Saffat Quasem; Sandeep K. Gupta 001 (VTS, 2004)

Defect and Error Tolerance in the Presence of Massive Numbers of Defects. - Melvin A. Breuer; Sandeep K. Gupta 001; T. M. Mak (IEEE Des. Test Comput., 2004)

A framework for systematic evaluation of multicast congestion control protocols. - Karim Seada; Ahmed Helmy; Sandeep Gupta 001 (IEEE J. Sel. Areas Commun., 2004)

The STRESS method for boundary-point performance analysis of end-to-end multicast timer-suppression mechanisms. - Ahmed Helmy; Sandeep Gupta 001; Deborah Estrin (IEEE/ACM Trans. Netw., 2004)

Selection of Paths for Delay Testing. - I-De Huang; Sandeep K. Gupta 001 (Asian Test Symposium, 2005)

Threshold testing: Covering bridging and other realistic faults. - Zhigang Jiang; Sandeep K. Gupta 001 (Asian Test Symposium, 2005)

A Methodology to Compute Bounds on Crosstalk Effects in Arbitrary Interconnects. - Wichian Sirisaengtaksin; Sandeep K. Gupta 001 (Asian Test Symposium, 2005)

TCP vs. TCP: a systematic study of adverse impact of short-lived TCP flows on long-lived TCP flows. - Shirin Ebrahimi-Taghizadeh; Ahmed Helmy; Sandeep Gupta 001 (INFOCOM, 2005)

Multiple tests for each gate delay fault: higher coverage and lower test application cost. - Shahdad Irajpour; Sandeep K. Gupta 001; Melvin A. Breuer (ITC, 2005)

FOTG: fault-oriented stress testing of IP multicast. - Ahmed Helmy; Sandeep Gupta 001 (IEEE Commun. Lett., 2005)

Test Generation for Weak Resistive Bridges. - Shahdad Irajpour; Sandeep K. Gupta 001; Melvin A. Breuer (ATS, 2006)

Diagnosis of delay faults due to resistive bridges, delay variations and defects. - Lei Wang; Sandeep K. Gupta 001; Melvin A. Breuer (ATS, 2006)

STAX: statistical crosstalk target set compaction. - Shahin Nazarian; Massoud Pedram; Sandeep K. Gupta 001; Melvin A. Breuer (DATE Designers' Forum, 2006)

A theory of Error-Rate Testing. - Shideh Shahidi; Sandeep K. Gupta 001 (ICCD, 2006)

Low-Cost Scan-Based Delay Testing of Latch-Based Circuits with Time Borrowing. - Kun Young Chung; Sandeep K. Gupta 001 (VTS, 2006)

LT-RTPG: a new test-per-scan BIST TPG for low switching activity. - Seongmoon Wang; Sandeep K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006)

On Generating Vectors That Invoke High Circuit Delays - Delay Testing and Dynamic Timing Analysis. - I-De Huang; Sandeep K. Gupta 001 (ATS, 2007)

Improving Timing-Independent Testing of Crosstalk Using Realistic Assumptions on Delay Faults. - Shahdad Irajpour; Sandeep K. Gupta 001; Melvin A. Breuer (ATS, 2007)

Performance Analysis of Wireless MAC Protocols Using a Search Based Framework. - Shamim Begum; Sandeep Gupta 001; Ahmed Helmy (MASCOTS, 2007)

A Re-design Technique for Datapath Modules in Error Tolerant Applications. - Doochul Shin; Sandeep K. Gupta 001 (ATS, 2008)

A Multi-valued Algebra for Capacitance Induced Crosstalk Delay Faults. - Arani Sinha; Sandeep K. Gupta 001; Melvin A. Breuer (ATS, 2008)

Matrix Inversion on a PIM (Processor-in-Memory). - Jae Chul Cha; Sandeep K. Gupta 001 (CSSE (3), 2008)

Multi-Vector Tests: A Path to Perfect Error-Rate Testing. - Shideh Shahidi; Sandeep Gupta 001 (DATE, 2008)

Characterization of granularity and redundancy for SRAMs for optimal yield-per-area. - Jae Chul Cha; Sandeep K. Gupta 001 (ICCD, 2008)

Data Partitioning and Placement Schemes for Matrix Multiplications on a PIM Architecture. - Jae Chul Cha; Sandeep K. Gupta 001 (ISPDC, 2008)

On Accelerating Path Delay Fault Simulation of Long Test Sequences. - I-De Huang; Yi-Shing Chang; Suriyaprakash Natarajan; Ramesh Sharma; Sandeep K. Gupta 001 (ITC, 2008)

An Industrial Case Study of Sticky Path-Delay Faults. - I-De Huang; Yi-Shing Chang; Sandeep K. Gupta 001; Sreejit Chakravarty (VTS, 2008)

An Efficient Data-Distribution Mechanism in a Processor-In-Memory (PIM) Architecture Applied to Motion Estimation. - Jung-Yup Kang; Sandeep K. Gupta 001; Jean-Luc Gaudiot (IEEE Trans. Computers, 2008)

SIRUP: Switch Insertion in RedUndant Pipeline Structures for Yield and Yield/Area Improvement. - Mohammad Mirza-Aghatabar; Melvin A. Breuer; Sandeep K. Gupta 001 (Asian Test Symposium, 2009)

Tolerance of performance degrading faults for effective yield improvement. - Tong-Yu Hsieh; Melvin A. Breuer; Murali Annavaram; Sandeep K. Gupta 001; Kuen-Jong Lee (ITC, 2009)

Modeling and test generation for worst-case performance evaluation of MAC protocols for wireless ad hoc networks. - Shamim Begum; Ahmed Helmy; Sandeep Gupta 001 (MASCOTS, 2009)

Efficient Scheduling of Path Delay Tests for Latch-Based Circuits. - Kun Young Chung; Sandeep K. Gupta 001 (VTS, 2009)

Threshold Testing: Improving Yield for Nanoscale VLSI. - Zhigang Jiang; Sandeep K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009)

HYPER: A Heuristic for Yield/Area imProvEment Using Redundancy in SoC. - Mohammad Mirza-Aghatabar; Melvin A. Breuer; Sandeep K. Gupta 001 (Asian Test Symposium, 2010)

Algorithms to maximize yield and enhance yield/area of pipeline circuitry by insertion of switches and redundant modules. - Mohammad Mirza-Aghatabar; Melvin A. Breuer; Sandeep K. Gupta 001 (DATE, 2010)

Approximate logic synthesis for error tolerant applications. - Doochul Shin; Sandeep K. Gupta 001 (DATE, 2010)

Design and test of latch-based circuits to maximize performance, yield, and delay test quality. - Kun Young Chung; Sandeep K. Gupta 001 (ITC, 2010)

Modeling the interactions between MAC and higher layer: A systematic approach to generate high-level scenarios from MAC-layer scenarios. - Shamim Begum; Ahmed Helmy; Sandeep Gupta 001 (ACM Trans. Model. Comput. Simul., 2010)

Yield-per-Area Optimization for 6T-SRAMs Using an Integrated Approach to Exploit Spares and ECC to Efficiently Combat High Defect and Soft-Error Rates. - Jae Chul Cha; Sandeep K. Gupta 001 (Asian Test Symposium, 2011)

On Generating Vectors for Accurate Post-Silicon Delay Characterization. - Prasanjeet Das; Sandeep K. Gupta 001 (Asian Test Symposium, 2011)

A new circuit simplification method for error tolerant applications. - Doochul Shin; Sandeep K. Gupta 001 (DATE, 2011)

A novel software-based defect-tolerance approach for application-specific embedded systems. - Da Cheng; Sandeep Gupta 001 (ICCD, 2011)

Efficient Trojan Detection via Calibration of Process Variations. - Byeongju Cha; Sandeep K. Gupta 001 (Asian Test Symposium, 2012)

Salvaging chips with caches beyond repair. - Hsunwei Hsiung; Byeongju Cha; Sandeep K. Gupta 001 (DATE, 2012)

A systematic methodology to improve yield per area of highly-parallel CMPs. - Da Cheng; Sandeep K. Gupta 001 (DFT, 2012)

Towards systematic roadmaps for networked systems. - Bin Liu 004; Hsunwei Hsiung; Da Cheng; Ramesh Govindan; Sandeep Gupta 001 (HotNets, 2012)

Theory of redundancy for logic circuits to maximize yield/area. - Mohammad Mirza-Aghatabar; Melvin A. Breuer; Sandeep K. Gupta 001; Shahin Nazarian (ISQED, 2012)

A design flow to maximize yield/area of physical devices via redundancy. - Mohammad Mirza-Aghatabar; Melvin A. Breuer; Sandeep K. Gupta 001 (ITC, 2012)

A New March Test for Process-Variation Induced Delay Faults in SRAMs. - Da Cheng; Hsunwei Hsiung; Bin Liu 004; Jianing Chen; Jia Zeng; Ramesh Govindan; Sandeep K. Gupta 001 (Asian Test Symposium, 2013)

Interplay of Failure Rate, Performance, and Test Cost in TCAM under Process Variations. - Hsunwei Hsiung; Da Cheng; Bin Liu 004; Ramesh Govindan; Sandeep K. Gupta 001 (Asian Test Symposium, 2013)

An energy and deadline aware resource provisioning, scheduling and optimization framework for cloud systems. - Yue Gao; Yanzhi Wang; Sandeep K. Gupta 001; Massoud Pedram (CODES+ISSS, 2013)

Trojan detection via delay measurements: a new approach to select paths and vectors to maximize effectiveness and minimize cost. - Byeongju Cha; Sandeep K. Gupta 001 (DATE, 2013)

Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors. - Yue Gao; Sandeep K. Gupta 001; Melvin A. Breuer (DATE, 2013)

Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuits. - Prasanjeet Das; Sandeep K. Gupta 001 (ICCD, 2013)

Extending pre-silicon delay models for post-silicon tasks: Validation, diagnosis, delay testing, and speed binning. - Prasanjeet Das; Sandeep K. Gupta 001 (VTS, 2013)

A Resizing Method to Minimize Effects of Hardware Trojans. - Byeongju Cha; Sandeep K. Gupta 001 (ATS, 2014)

Optimal Redundancy Designs for CNFET-Based Circuits. - Da Cheng; Fangzhou Wang; Feng Gao; Sandeep K. Gupta 001 (ATS, 2014)

SRAM Array Yield Estimation under Spatially-Correlated Process Variation. - Jizhe Zhang; Sandeep Gupta 001 (ATS, 2014)

An energy-aware fault tolerant scheduling framework for soft error resilient cloud computing systems. - Yue Gao; Sandeep K. Gupta 001; Yanzhi Wang; Massoud Pedram (DATE, 2014)

Efficient post-silicon validation via segmentation of process variation envelope - Global vs local variations. - Prasanjeet Das; Sandeep K. Gupta 001 (ISQED, 2014)

Optimizing redundancy design for chip-multiprocessors for flexible utility functions. - Da Cheng; Sandeep K. Gupta 001 (ITC, 2014)

Maximizing Yield per Area of Highly Parallel CMPs Using Hardware Redundancy. - Da Cheng; Sandeep K. Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

Analysis and optimization of soft error tolerance strategies for real-time systems. - Bowen Zheng 001; Yue Gao; Qi Zhu 002; Sandeep K. Gupta 001 (CODES+ISSS, 2015)

PPB: Partially-working processors binning for maximizing wafer utilization. - Da Cheng; Sandeep K. Gupta 001 (VTS, 2015)

A multi-layered methodology for defect-tolerance of datapath modules in processors. - Hsunwei Hsiung; Sandeep K. Gupta 001 (VTS, 2015)

Yield estimation and statistical design of memristor cross-point memory systems. - Jizhe Zhang; Sandeep K. Gupta 001 (ISQED, 2016)

Using hardware testing approaches to improve software testing: Undetectable mutant identification. - Jianwei Zhang; Sandeep K. Gupta 001 (VTS, 2016)

SRAM yield-per-area optimization under spatially-correlated process variation. - Jizhe Zhang; Sandeep K. Gupta 001 (VTS, 2016)

Process variation oriented delay testing of SRAMs. - Xuan Zuo; Sandeep K. Gupta 001 (VTS, 2016)

Wordline overdriving test: An effective predictive testing method for SRAMs against BTI aging. - Jizhe Zhang; Sandeep K. Gupta 001 (ISQED, 2017)

Accelerating Circuit Realization via a Collaborative Gateway of Innovations. - Ian J. Taylor; Adam Brinckman; Ewa Deelman; Rafael Ferreira da Silva; Sandeep Gupta 001; Jarek Nabrzyski; Soowang Park; Karan Vahi (IWSG, 2017)

Keynote address tribute to Professor Mel Breuer: Contributions to CAD and Test. - Sandeep Gupta 001; Miron Abramovici; Magdy Abadir; Sridhar Narayanan (VTS, 2017)

Asymmetric sizing: An effective design approach for SRAM cells against BTI aging. - Xuan Zuo; Sandeep K. Gupta 001 (VTS, 2017)

Multi-cell characterization: Developing robust cells and abstraction for Rapid Single Flux Quantum (RSFQ) Logic. - Fangzhou Wang; Sandeep Gupta 001 (ITC, 2019)

A Secure Gateway for Enabling ASIC Design Collaborations. - Steve Bogol; Paul R. Brenner; Adam Brinckman; Ewa Deelman; Rafael Ferreira da Silva; Sandeep Gupta 001; Jarek Nabrzyski; Soowang Park; Damian Perez; Mats Rynge; Ian J. Taylor; Karan Vahi; et al. (IWSG, 2019)

Cache Design for Yield-per-Area Maximization: Switchable Spare Columns with Disabling (SSC-Disable). - Soowang Park; Sandeep K. Gupta 001 (VTS, 2019)

Automatic Test Pattern Generation for timing verification and delay testing of RSFQ circuits. - Fangzhou Wang; Sandeep Gupta 001 (VTS, 2019)

A New Method for Software Test Data Generation Inspired by D-algorithm. - Jianwei Zhang; Sandeep K. Gupta 001; William G. J. Halfond (VTS, 2019)

Collaborative circuit designs using the CRAFT repository. - Adam Brinckman; Ewa Deelman; Sandeep Gupta 001; Jarek Nabrzyski; Soowang Park; Rafael Ferreira da Silva; Ian J. Taylor; Karan Vahi (Future Gener. Comput. Syst., 2019)

Data-driven fault model development for superconducting logic. - Mingye Li; Fangzhou Wang; Sandeep Gupta 001 (ITC, 2020)

Aging-resilient SRAM design: an end-to-end framework. - Xuan Zuo; Sandeep K. Gupta 001 (VTS, 2020)

HW-BCP: A Custom Hardware Accelerator for SAT Suitable for Single Chip Implementation for Large Benchmarks. - Soowang Park; Jae-Won Nam; Sandeep K. Gupta 001 (ASP-DAC, 2021)

From Specification to Silicon: Towards Analog/Mixed-Signal Design Automation using Surrogate NN Models with Transfer Learning. - Juzheng Liu; Shiyu Su; Meghna Madhusudan; Mohsen Hassanpourghadi; Samuel Saunders; Qiaochu Zhang; Rezwan A. Rasul; Yaguang Li; Jiang Hu; Arvind Kumar Sharma; Sachin S. Sapatnekar; Ramesh Harjani; et al. (ICCAD, 2021)

Fault-coverage Maximizing March Tests for Memory Testing. - Feng Yun; Yunkun Lin; Lou Yunfei; Lei Gao; Vaibhav Gera; Boxuan Li; Vennela Chowdary Nekkanti; Aditya Rajendra Pharande; Kunal Sheth; Meghana Thommondru; Guizhong Ye; Sandeep Gupta 001 (ITC, 2022)

Memristor-Specific Failures: New Verification Methods and Emerging Test Problems. - Baishakhi Rani Biswas; Sandeep Gupta 001 (VTS, 2022)

Methods for testing path delay and static faults in RSFQ circuits. - Mingye Li; Fangzhou Wang; Sandeep Gupta 001 (VTS, 2022)

Design for testability (DFT) for RSFQ circuits. - Mingye Li; Yunkun Lin; Sandeep Gupta 001 (VTS, 2023)

Challenges and Unexplored Frontiers in Electronic Design Automation for Superconducting Digital Logic. - Sasan Razmkhah; Robert S. Aviles; Mingye Li; Sandeep Gupta 001; Peter A. Beerel; Massoud Pedram (DATE, 2024)

A Novel Multi-Objective Optimization Framework for Analog Circuit Customization. - Mutian Zhu; Mohsen Hassanpourghadi; Qiaochu Zhang; Mike Shuo-Wei Chen; Anthony F. J. Levi; Sandeep Gupta 001 (DATE, 2024)

Predictive Testing for Aging in SRAMs and Mitigation. - Yunkun Lin; Mingye Li; Sandeep Gupta 001 (ITC, 2024)

Synthesizable 10-bit Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adder with 0.012mm2 Active Area in 12nm FinFET. - Qiaochu Zhang; Shiyu Su; Baishakhi Rani Biswas; Sandeep Gupta 001; Mike Shuo-Wei Chen (VLSI Technology and Circuits, 2024)

Built in self test (BIST) for RSFQ circuits. - Mingye Li; Yunkun Lin; Sandeep Gupta 001 (VTS, 2024)

Systematic Generation of Memristor-Transistor Single-Phase Combinational Logic Cells. - Baishakhi Rani Biswas; Claire Yuan; Fangzhou Wang; Sandeep Gupta 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2024)

Stochastic TDC Using Common-Mode Time Dithering and Passive Approximate Adders. - Shiyu Su; Qiaochu Zhang; Baishakhi Rani Biswas; Sandeep K. Gupta 001; Mike Shuo-Wei Chen (IEEE J. Solid State Circuits, 2025)