A 64-MHz clock-rate ΣΔ ADC with 88-dB SNDR and -105-dB IM3 distortion at a 1.5-MHz signal frequency. - Sandeep K. Gupta 003; Victor Fong (IEEE J. Solid State Circuits, 2002)

A 1-GS/s 11-bit ADC With 55-dB SNDR, 250-mW Power Realized by a High Bandwidth Scalable Time-Interleaved Architecture. - Sandeep K. Gupta 003; Michael A. Inerfield; Jingbo Wang (IEEE J. Solid State Circuits, 2006)