Wrapper design for embedded core test. - Yervant Zorian; Erik Jan Marinissen; Maurice Lousberg; Sandeep Kumar Goel (ITC, 2000)

A novel test time reduction algorithm for test architecture design for core-based system chips. - Sandeep Kumar Goel; Erik Jan Marinissen (ETW, 2002)

Effective and Efficient Test Architecture Design for SOCs. - Sandeep Kumar Goel; Erik Jan Marinissen (ITC, 2002)

Hierarchical Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. - Sandeep Kumar Goel; Bart Vermeulen (ITC, 2002)

Test Resource Optimization for Multi-Site Testing of SOCs Under ATE Memory Depth Constraints. - Vikram Iyengar; Sandeep Kumar Goel; Erik Jan Marinissen; Krishnendu Chakrabarty (ITC, 2002)

Core-Based Scan Architecture for Silicon Debug. - Bart Vermeulen; Tom Waayers; Sandeep Kumar Goel (ITC, 2002)

Cluster-Based Test Architecture Design for System-on-Chip. - Sandeep Kumar Goel; Erik Jan Marinissen (VTS, 2002)

Design for Debug: Catching Design Errors in Digital Chips. - Bart Vermeulen; Sandeep Kumar Goel (IEEE Des. Test Comput., 2002)

Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization. - Sandeep Kumar Goel; Erik Jan Marinissen (DATE, 2003)

Control-aware test architecture design for modular SOC testing. - Sandeep Kumar Goel; Erik Jan Marinissen (ETW, 2003)

A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips. - Sandeep Kumar Goel; Erik Jan Marinissen (J. Electron. Test., 2003)

Data Invalidation Analysis for Scan-Based Debug on Multiple-Clock System Chips. - Sandeep Kumar Goel; Bart Vermeulen (J. Electron. Test., 2003)

SOC test architecture design for efficient utilization of test bandwidth. - Sandeep Kumar Goel; Erik Jan Marinissen (ACM Trans. Design Autom. Electr. Syst., 2003)

Automatic generation of breakpoint hardware for silicon debug. - Bart Vermeulen; Mohammad Zalfany Urfianto; Sandeep Kumar Goel (DAC, 2004)

Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip. - Sandeep Kumar Goel; Kuoshu Chiu; Erik Jan Marinissen; Toan Nguyen; Steven Oostdijk (DATE, 2004)

User-constrained test architecture design for modular SOC testing. - Ludovic A. Krundel; Sandeep Kumar Goel; Erik Jan Marinissen; Marie-Lise Flottes; Bruno Rouzeyre (ETS, 2004)

IEEE P1500-Compliant Test Wrapper Design for Hierarchical Cores. - Anuja Sehgal; Sandeep Kumar Goel; Erik Jan Marinissen; Krishnendu Chakrabarty (ITC, 2004)

On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips. - Sandeep Kumar Goel; Erik Jan Marinissen (DATE, 2005)

Test scheduling for modular SOCs in an abort-on-fail environment. - Urban Ingelsson; Sandeep Kumar Goel; Erik Larsson; Erik Jan Marinissen (ETS, 2005)

Fault detection and diagnosis with parity trees for space compaction of test responses. - Harald P. E. Vranken; Sandeep Kumar Goel; Andreas Glowatz; Jürgen Schlöffel; Friedrich Hapke (DAC, 2006)

Hierarchy-aware and area-efficient test infrastructure design for core-based system chips. - Anuja Sehgal; Sandeep Kumar Goel; Erik Jan Marinissen; Krishnendu Chakrabarty (DATE, 2006)

Testing and Diagnosis of Power Switches in SOCs. - Sandeep Kumar Goel; Maurice Meijer; José Pineda de Gyvez (ETS, 2006)

Efficient testing and diagnosis of faulty power switches in SOCs. - Sandeep Kumar Goel; Maurice Meijer; José Pineda de Gyvez (IET Comput. Digit. Tech., 2007)

Accurate measurement of small delay defect coverage of test patterns. - Narendra Devta-Prasanna; Sandeep Kumar Goel; Arun Gunda; Mark Ward; P. Krishnamurthy (ITC, 2009)

Comparing the effectiveness of deterministic bridge fault and multiple-detect stuck fault patterns for physical bridge defects: A simulation and silicon study. - Sandeep Kumar Goel; Narendra Devta-Prasanna; Mark Ward (ITC, 2009)

Effective and Efficient Test Pattern Generation for Small Delay Defect. - Sandeep Kumar Goel; Narendra Devta-Prasanna; Ritesh P. Turakhia (VTS, 2009)

Bridging DFM Analysis and Volume Diagnostics for Yield Learning - A Case Study. - Ritesh P. Turakhia; Mark Ward; Sandeep Kumar Goel; Brady Benware (VTS, 2009)

Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling. - Sandeep Kumar Goel; Erik Jan Marinissen; Anuja Sehgal; Krishnendu Chakrabarty (IEEE Trans. Computers, 2009)

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. - Sandeep Kumar Goel; Krishnendu Chakrabarty; Mahmut Yilmaz; Ke Peng; Mohammad Tehranipoor (Asian Test Symposium, 2010)

Test-architecture optimization for TSV-based 3D stacked ICs. - Brandon Noia; Sandeep Kumar Goel; Krishnendu Chakrabarty; Erik Jan Marinissen; Jouke Verbree (ETS, 2010)

Multi-visit TAMs to Reduce the Post-Bond Test Length of 2.5D-SICs with a Passive Silicon Interposer Base. - Chun-Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng-Wen Wu (Asian Test Symposium, 2011)

Automation of 3D-DfT Insertion. - Sergej Deutsch; Vivek Chickermane; Brion L. Keller; Subhasish Mukherjee; Mario Konijnenburg; Erik Jan Marinissen; Sandeep Kumar Goel (Asian Test Symposium, 2011)

DfT Architecture for 3D-SICs with Multiple Towers. - Chun-Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng-Wen Wu (ETS, 2011)

Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. - Chun-Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng-Wen Wu (ITC, 2011)

Test-Architecture Optimization and Test Scheduling for TSV-Based 3-D Stacked ICs. - Brandon Noia; Krishnendu Chakrabarty; Sandeep Kumar Goel; Erik Jan Marinissen; Jouke Verbree (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011)

EDA solutions to new-defect detection in advanced process technologies. - Erik Jan Marinissen; Gilbert Vandling; Sandeep Kumar Goel; Friedrich Hapke; Jason Rivers; Nikolaus Mittermaier; Swapnil Bahl (DATE, 2012)

Test challenges in designing complex 3D chips: What in on the horizon for EDA industry?: Designer track. - Sandeep Kumar Goel (ICCAD, 2012)

DfT architecture and ATPG for Interconnect tests of JEDEC Wide-I/O memory-on-logic die stacks. - Sergej Deutsch; Brion L. Keller; Vivek Chickermane; Subhasish Mukherjee; Navdeep Sood; Sandeep Kumar Goel; Ji-Jan Chen; Ashok Mehta; Frank Lee 004; Erik Jan Marinissen (ITC, 2012)

Test and debug strategy for TSMC CoWoS™ stacking process based heterogeneous 3D IC: A silicon case study. - Sandeep Kumar Goel; Saman Adham; Min-Jer Wang; Ji-Jan Chen; Tze-Chiang Huang; Ashok Mehta; Frank Lee 004; Vivek Chickermane; Brion L. Keller; Thomas Valind; Subhasish Mukherjee; Navdeep Sood; et al. (ITC, 2013)

Small-Delay Defect Coverage Metrics. - Narendra Devta-Prasanna; Sandeep Kumar Goel (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. - Sandeep Kumar Goel; Krishnendu Chakrabarty (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. - Sandeep Kumar Goel; Narendra Devta-Prasanna (Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, 2014)

Design-for-diagnosis: Your safety net in catching design errors in known good dies in CoWoSTM/3D ICs. - Sandeep Kumar Goel; Min-Jer Wang; Saman Adham; Ashok Mehta; Frank Lee 004 (VLSI-DAT, 2014)

Low-Cost Post-Bond Testing of 3-D ICs Containing a Passive Silicon Interposer Base. - Chun-Chuan Chi; Erik Jan Marinissen; Sandeep Kumar Goel; Cheng-Wen Wu (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Efficient observation-point insertion for diagnosability enhancement in digital circuits. - Zipeng Li; Sandeep Kumar Goel; Frank Lee 004; Krishnendu Chakrabarty (ITC, 2015)

Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption. - Urban Ingelsson; Sandeep Kumar Goel; Erik Larsson; Erik Jan Marinissen (IEEE Trans. Computers, 2015)

A 7nm 4GHz Arm®-core-based CoWoS® Chiplet Design for High Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Tom Chen 002; Wen-Hung Huang; Jack Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (VLSI Circuits, 2019)

A 7-nm 4-GHz Arm¹-Core-Based CoWoS¹ Chiplet Design for High-Performance Computing. - Mu-Shan Lin; Tze-Chiang Huang; Chien-Chun Tsai; King-Ho Tam; Kenny Cheng-Hsiang Hsieh; Ching-Fang Chen; Wen-Hung Huang; Chi-Wei Hu; Yu-Chi Chen; Sandeep Kumar Goel; Chin-Ming Fu; Stefan Rusu; et al. (IEEE J. Solid State Circuits, 2020)

Challenges and Solutions for 3D Fabric: A Foundry Perspective. - Sandeep Kumar Goel (ISPD, 2022)

Innovative Practices Track: Test of 3D ICs & Chiplets. - Sandeep Kumar Goel; Sandeep Pendharkar; Chunsheng Liu (VTS, 2022)

A Case Study on IEEE 1838 Compliant Multi-Die 3DIC DFT Implementation. - Anshuman Chandra; Moiz Khan; Ankita Patidar; Fumiaki Takashima; Sandeep Kumar Goel; Bharath Shankaranarayanan; Vuong Nguyen; Vistrita Tyagi; Manish Arora (ITC, 2023)

Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Impact. - Sandeep Kumar Goel; Ankita Patidar; Frank Lee 004 (ETS, 2024)

Handling Die-to-Die I/O Pads for 3DIC Interconnect Tests. - Sandeep Kumar Goel; Moiz Khan; Ankita Patidar; Frank Lee 004; Vuong Nguyen; Bharath Shankaranarayanan; Doo Kim; Manish Arora (ITC, 2024)

Physical-Aware Interconnect Test for Multi-Die Systems Using 3Dblox Open Standard. - Sandeep Kumar Goel; Ankita Patidar; Moiz Khan; Frank Lee 004; Anshuman Chandra; Martin Keim; Naim Lemar; Jonathan Gaudet; Quoc Phan; Vidya Neerkundar (ITC, 2024)