Efficient nanoscale VLSI standard cell library characterization using a novel delay model. - Sandeep Miryala; Baljit Kaur; Bulusu Anand; Sanjeev Manhas (ISQED, 2011)

IR-drop analysis of graphene-based power distribution networks. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2012)

NBTI effects on tree-like clock distribution networks. - Wei Liu 016; Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2012)

A verilog-a model for reconfigurable logic gates based on graphene pn-junctions. - Sandeep Miryala; Mehrdad Montazeri; Andrea Calimera; Enrico Macii; Massimo Poncino (DATE, 2013)

Delay model for reconfigurable logic gates based on graphene PN-junctions. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2013)

Exploration of different implementation styles for graphene-based reconfigurable gates. - Sandeep Miryala; Andrea Calimera; Massimo Poncino; Enrico Macii (ICICDT, 2013)

An efficient method for ECSM characterization of CMOS inverter in nanometer range technologies. - Baljit Kaur; Sandeep Miryala; S. K. Manhas; Bulusu Anand (ISQED, 2013)

Investigating the behavior of physical defects in pn-junction based reconfigurable graphene devices. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino; Letícia Maria Veiras Bolzani Poehls (LATW, 2013)

Power modeling and characterization of Graphene-based logic gates. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (PATMOS, 2013)

Ultra Low-Power Computation via Graphene-Based Adiabatic Logic Gates. - Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (DSD, 2014)

Modeling of Physical Defects in PN Junction Based Graphene Devices. - Sandeep Miryala; Matheus Oleiro; Letícia Maria Bolzani Pöhls; Andrea Calimera; Enrico Macii; Massimo Poncino (J. Electron. Test., 2014)

Row-based body-bias assignment for dynamic thermal clock-skew compensation. - Valerio Tenace; Sandeep Miryala; Andrea Calimera; Alberto Macii; Enrico Macii; Massimo Poncino (Microelectron. J., 2014)

CAD Solutions for Graphene Based Nanoelectronic Circuits and Systems. - Sandeep Miryala (2014)

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino; Luca Gaetano Amarù; Giovanni De Micheli; Pierre-Emmanuel Gaillardon (ACM Great Lakes Symposium on VLSI, 2015)

Design and Characterization of Analog-to-Digital Converters using Graphene P-N Junctions. - Roberto Giorgio Rizzo; Sandeep Miryala; Andrea Calimera; Enrico Macii; Massimo Poncino (ACM Great Lakes Symposium on VLSI, 2015)

Ultra-low power circuits using graphene p-n junctions and adiabatic computing. - Sandeep Miryala; Valerio Tenace; Andrea Calimera; Enrico Macii; Massimo Poncino (Microprocess. Microsystems, 2015)

A novel energy-efficient self-correcting methodology employing INWE. - Chaudhry Indra Kumar; Arvind Kumar Sharma; Sandeep Miryala; Anand Bulusu (SMACD, 2016)

Schottky-barrier graphene nanoribbon field-effect transistors-based field-programmable gate array's configurable logic block and routing switch. - Sayed Ali Seif Kashani; Hossein Karimiyan Alidash; Sandeep Miryala (IET Circuits Devices Syst., 2017)

A 1.2-V 6-GHz Dual-Path Charge-Pump PLL Frequency Synthesizer for Quantum Control and Readout in CMOS 65-nm Process. - Vamshi Manthena; Sandeep Miryala; Grzegorz Deptuch; Gabriella Carini (UEMCON, 2020)

A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. - Dinesh Kushwaha; Aditya Sharma; Neha Gupta; Ritik Raj; Ashish Joshi; Jwalant Mishra; Rajat Kohli; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (ISCAS, 2022)

Design and Challenges of Edge Computing ASICs on Front-End Electronics. - Sandeep Miryala; Gabriella Carini; Grzegorz Deptuch; Jin Huang; Srinivas Katkoori; Piotr Maj; Soumyajit Mandal; Yihui Ren 001; Md. Adnan Zaman (ISQED, 2022)

Peak Prediction Using Multi Layer Perceptron (MLP) for Edge Computing ASICs Targeting Scientific Applications. - Sandeep Miryala; Md. Adnan Zaman; Sandeep Mittal; Yihui Ren 001; Grzegorz Deptuch; Gabriella Carini; Sioan Zohar; Shinjae Yoo; Jack Fried; Jin Huang; Srinivas Katkoori (ISQED, 2022)

Investigation of Timing Properties for an Event Driven with Access and Reset Decoder Readout Architecture for a Pixel Array. - Dominik Gorni; Grzegorz Deptuch; Sandeep Miryala (PRIME, 2022)

An Energy-Efficient High CSNR XNOR and Accumulation Scheme for BNN. - Dinesh Kushwaha; Ashish Joshi; Chaudhry Indra Kumar; Neha Gupta; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 2.56-GS/s 12-bit 8x-Interleaved ADC With 156.6-dB FoMS in 65-nm CMOS. - Liang Fang; Xianshan Wen; Tao Fu; Guanhua Wang; Sandeep Miryala; Tiehui Ted Liu; Ping Gui (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Energy-Efficient Multi-bit Current-based Analog Compute-In-Memory Architecture and design Methodology. - Dinesh Kushwaha; Ashish Joshi; Neha Gupta; Aditya Sharma; Sandeep Miryala; Rajiv V. Joshi; Sudeb Dasgupta; Anand Bulusu (VLSID, 2023)