Intrinsic 1/f device noise reduction and its effect on phase noise in CMOS ring oscillators. - Sander L. J. Gierkink; Eric A. M. Klumperink; Arnoud P. van der Wel; Gian Hoogzaad; Ed A. J. M. van Tuijl; Bram Nauta (IEEE J. Solid State Circuits, 1999)

Reducing MOSFET 1/f noise and power consumption by switched biasing. - Eric A. M. Klumperink; Sander L. J. Gierkink; Arnoud P. van der Wel; Bram Nauta (IEEE J. Solid State Circuits, 2000)

A coupled sawtooth oscillator combining low jitter with high control linearity. - Sander L. J. Gierkink; Ed van Tuijl (IEEE J. Solid State Circuits, 2002)

Frequency dependence on bias current in 5 GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. - Salvatore Levantino; Carlo Samori; Andrea Bonfanti; Sander L. J. Gierkink; Andrea L. Lacaita; Vito Boccuzzi (IEEE J. Solid State Circuits, 2002)

Differentially "bathtub"-tuned CMOS VCO using inductively coupled varactors. - Sander L. J. Gierkink; Robert C. Frye; Vito Boccuzzi (ESSCIRC, 2003)

A low-phase-noise 5-GHz CMOS quadrature VCO using superharmonic coupling. - Sander L. J. Gierkink; Salvatore Levantino; Robert C. Frye; Carlo Samori; Vito Boccuzzi (IEEE J. Solid State Circuits, 2003)

A 3.5GHz integer-N PLL with dual on-chip loop filters and VCO tune ports for fast low-IF/zero-IF LO switching in an 802.11 transceiver. - Sander L. J. Gierkink; Dandan Li; Robert C. Frye; Vito Boccuzzi (CICC, 2004)

A robust 43-GHz VCO in CMOS for OC-768 SONET applications. - Arnoud P. van der Wel; Sander L. J. Gierkink; Robert C. Frye; Vito Boccuzzi; Bram Nauta (IEEE J. Solid State Circuits, 2004)

A 3.5-GHz PLL for fast low-IF/zero-IF LO switching in an 802.11 transceiver. - Sander L. J. Gierkink; Dandan Li; Robert C. Frye; Vito Boccuzzi (IEEE J. Solid State Circuits, 2005)

A 2.5Gb/s Burst-Mode CDR based on a 1/8th rate Dual Pulse Ring Oscillator. - Sander L. J. Gierkink (CICC, 2007)

A Process and Temperature Compensated Two-Stage Ring Oscillator. - Kadaba Lakshmikumar; Vinod Mukundagiri; Sander Laurentius Johannes Gierkink (CICC, 2007)

A 1V 15.6mW 1-2GHz -119dBc/Hz @ 200kHz clock multiplying DLL. - Sander Gierkink (CICC, 2008)

An 800MHz -122dBc/Hz-at-200kHz Clock Multiplier based on a Combination of PLL and Recirculating DLL. - Sander Gierkink (ISSCC, 2008)

A 2.5 Gb/s Run-Length-Tolerant Burst-Mode CDR Based on a 1/8th-Rate Dual Pulse Ring Oscillator. - Sander L. J. Gierkink (IEEE J. Solid State Circuits, 2008)

Low-Spur, Low-Phase-Noise Clock Multiplier Based on a Combination of PLL and Recirculating DLL With Dual-Pulse Ring Oscillator and Self-Correcting Charge Pump. - Sander L. J. Gierkink (IEEE J. Solid State Circuits, 2008)

A 3-level PWM ADSL2+ CO line driver. - Sander Gierkink; Kadaba Lakshmikumar; Vinod Mukundagiri; Drahoslav Lím; Arnold Muralt; Fred Larsen (CICC, 2009)