RISC-V Half Precision Floating Point Instruction Set Extensions and Co-processor. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; A. David Selvakumar (VDAT, 2019)

A Novel Parametrized Fused Division and Square-Root POSIT Arithmetic Architecture. - Aneesh Raveendran; Sandra Jean; J. Mervin; Vivian Desalphine; David Selvakumar (VLSID, 2020)

P-FMA: A Novel Parameterized Posit Fused Multiply-Accumulate Arithmetic Processor. - Sandra Jean; Aneesh Raveendran; A. David Selvakumar; Gagandeep Kaur; Shankar G. Dharani; Shashikala Gunderao Pattanshetty; Vivian Desalphine (VLSID, 2021)

PositGen-A Verification Suite for Posit Arithmetic. - Annarao Kulkarni; Shashikala Gunderao Pattanshetty; Aneesh Raveendran; David Selvakumar; Sandra Jean; Vivian Desalphine (VLSID, 2021)