An Object Level Transformation Technique to Improve the Performance of Embedded Applications. - Sandro Bartolini; Cosimo Antonio Prete (SCAM, 2001)

Parallel architecture and compilation techniques: selection of workshop papers, guests' editors introduction. - Sandro Bartolini; Roberto Giorgi; Jelica Protic; Cosimo Antonio Prete; Mateo Valero (SIGARCH Comput. Archit. News, 2001)

A cache-aware program transformation technique suitable for embedded systems. - Sandro Bartolini; Cosimo Antonio Prete (Inf. Softw. Technol., 2002)

A Performance Evaluation of ARM ISA Extension for Elliptic Curve Cryptography over Binary Finite Fields. - Sandro Bartolini; Irina Branovic; Roberto Giorgi; Enrico Martinelli (SBAC-PAD, 2004)

A proposal for input-sensitivity analysis of profile-driven optimizations on embedded applications. - Sandro Bartolini; Cosimo Antonio Prete (SIGARCH Comput. Archit. News, 2004)

Guests editor's introduction. - Sandro Bartolini; Pierfrancesco Foglia; Cosimo Antonio Prete (SIGARCH Comput. Archit. News, 2005)

Optimizing instruction cache performance of embedded systems. - Sandro Bartolini; Cosimo Antonio Prete (ACM Trans. Embed. Comput. Syst., 2005)

Embedded processors and systems: Architectural issues and solutions for emerging applications. - Sandro Bartolini; Pierfrancesco Foglia; Cosimo Antonio Prete (J. Embed. Comput., 2006)

Issues in Embedded Single-Chip Multicore Architectures. - Sandro Bartolini; Roberto Giorgi (J. Embed. Comput., 2006)

Memory performance: dealing with applications, systems and architecture. - Sandro Bartolini; Pierfrancesco Foglia; Roberto Giorgi; Cosimo Antonio Prete (SIGARCH Comput. Archit. News, 2006)

Inclusion of a Montgomery Multiplier Unit into an Embedded Processor's Datapath to Speed-up Elliptic Curve Cryptography. - Sandro Bartolini; Cinzia Castagnini; Enrico Martinelli (IAS, 2007)

MEmory performance: DEaling with applications, systems and architecture. - Sandro Bartolini; Pierfrancesco Foglia; Cosimo Antonio Prete (SIGARCH Comput. Archit. News, 2007)

Instruction Cache Energy Saving Through Compiler Way-Placement. - Timothy M. Jones 001; Sandro Bartolini; Bruno De Bus; John Cavazos; Michael F. P. O'Boyle (DATE, 2008)

Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m). - Sandro Bartolini; Irina Branovic; Roberto Giorgi; Enrico Martinelli (IEEE Trans. Computers, 2008)

Instruction Set Extensions for Cryptographic Applications. - Sandro Bartolini; Roberto Giorgi; Enrico Martinelli (Cryptographic Engineering, 2009)

Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. - Sandro Bartolini; Pierfrancesco Foglia; Marco Solinas; Cosimo Antonio Prete (SBAC-PAD, 2010)

Link-time optimization for power efficiency in a tagless instruction cache. - Timothy M. Jones 001; Sandro Bartolini; Jonas Maebe; Dominique Chanet (CGO, 2011)

Eighth MEDEA Workshop. - Sandro Bartolini; Pierfrancesco Foglia; Cosimo Antonio Prete (Trans. High Perform. Embed. Archit. Compil., 2011)

A Simple On-Chip Optical Interconnection for Improving Performance of Coherency Traffic in CMPs. - Sandro Bartolini; Paolo Grani (DSD, 2012)

Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis. - Luca Ramini; Paolo Grani; Sandro Bartolini; Davide Bertozzi (DATE, 2013)

Olympic: A Hierarchical All-Optical Photonic Network for Low-Power Chip Multiprocessors. - Sandro Bartolini; Luca Lusnig; Enrico Martinelli (DSD, 2013)

Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs. - Sandro Bartolini; Paolo Grani (MES, 2013)

Assessing the energy break-even point between an optical NoC architecture and an aggressive electronic baseline. - Luca Ramini; Alberto Ghiribaldi; Paolo Grani; Sandro Bartolini; Hervé Tatenguem Fankem; Davide Bertozzi (DATE, 2014)

Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs. - Paolo Grani; Sandro Bartolini (HPCC/CSS/ICESS, 2014)

Solving Graph Partitioning Problems Arising in Tagless Cache Management. - Sandro Bartolini; Iacopo Casini; Paolo Detti (ISCO, 2014)

Towards compelling cases for the viability of silicon-nanophotonic technology in future manycore systems. - Luca Ramini; Hervé Tatenguem Fankem; Alberto Ghiribaldi; Paolo Grani; Marta Ortín-Obón; Anja Boos; Sandro Bartolini (NOCS, 2014)

Exploiting silicon photonics for energy-efficient heterogeneous parallel architectures. - Sandro Bartolini; José M. García 001 (Concurr. Comput. Pract. Exp., 2014)

Managing resources dynamically in hybrid photonic-electronic networks-on-chip. - Antonio García-Guirado; Ricardo Fernández-Pascual; José M. García 001; Sandro Bartolini (Concurr. Comput. Pract. Exp., 2014)

Design Options for Optical Ring Interconnect in Future Client Devices. - Paolo Grani; Sandro Bartolini (ACM J. Emerg. Technol. Comput. Syst., 2014)

Boosting multi-socket cache-coherency with low-latency silicon photonic interconnects. - Paolo Grani; Robert Hendry; Sandro Bartolini; Keren Bergman (ICNC, 2015)

PHAST Library - Enabling Single-Source and High Performance Code for GPUs and Multi-cores. - Biagio Peccerillo; Sandro Bartolini (HPCS, 2017)

Parallel Programming in Cyber-Physical Systems. - Sandro Bartolini; Biagio Peccerillo (Cyber-Physical Systems Security, 2018)

Exploring the relationship between architectures and management policies in the design of NUCA-based chip multicore systems. - Sandro Bartolini; Pierfrancesco Foglia; Cosimo Antonio Prete (Future Gener. Comput. Syst., 2018)

Augmented Virtuality for Coastal Management: A Holistic Use of In Situ and Remote Sensing for Large Scale Definition of Coastal Dynamics. - Sandro Bartolini; Alessandro Mecocci; Alessandro Pozzebon; Claudia Zoppetti; Duccio Bertoni; Giovanni Sarti; Andrea Caiti; Riccardo Costanzi; Filippo Catani; Andrea Ciampalini; Sandro Moretti (ISPRS Int. J. Geo Inf., 2018)

Scalable Path-Setup Scheme for All-Optical Dynamic Circuit Switched NoCs in Cache Coherent CMPs. - Paolo Grani; Sandro Bartolini (ACM J. Emerg. Technol. Comput. Syst., 2018)

Task-DAG Support in Single-Source PHAST Library: Enabling Flexible Assignment of Tasks to CPUs and GPUs in Heterogeneous Architectures. - Biagio Peccerillo; Sandro Bartolini (PMAM@PPoPP, 2019)

Parallel bitsliced AES through PHAST: a single-source high-performance library for multi-cores and GPUs. - Biagio Peccerillo; Sandro Bartolini; Çetin Kaya Koç (J. Cryptogr. Eng., 2019)

PHAST - A Portable High-Level Modern C++ Programming Library for GPUs and Multi-Cores. - Biagio Peccerillo; Sandro Bartolini (IEEE Trans. Parallel Distributed Syst., 2019)

Using PHAST to port Caffe library: First experiences and lessons learned. - Eduardo José Gómez-Hernández; Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José Manuel García Carrasco; Gregorio Bernabé (CoRR, 2020)

A General Framework for Accelerator Management Based on ISA Extension. - Elham Cheshmikhani; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2022)

Applying Intel's oneAPI to a machine learning case study. - Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José M. García 001; Gregorio Bernabé (Concurr. Comput. Pract. Exp., 2022)

Flexible task-DAG management in PHAST library: Data-parallel tasks and orchestration support for heterogeneous systems. - Biagio Peccerillo; Sandro Bartolini (Concurr. Comput. Pract. Exp., 2022)

Performance portability in a real world application: PHAST applied to Caffe. - Pablo Antonio Martínez; Biagio Peccerillo; Sandro Bartolini; José M. García 001; Gregorio Bernabé (Int. J. High Perform. Comput. Appl., 2022)

A survey on hardware accelerators: Taxonomy, trends, challenges, and perspectives. - Biagio Peccerillo; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (J. Syst. Archit., 2022)

Energy and Performance Improvements for Convolutional Accelerators Using Lightweight Address Translation Support. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (CF, 2023)

Software-Based Fault-Detection Technique for Object Tracking in Autonomous Vehicles. - Alessio Medaglini; Sandro Bartolini; Gianluca Mandò; Eduardo Quiñones; Sara Royuela (MECO, 2023)

Analysis and Optimization of Direct Convolution Execution on Multi-Core Processors. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

IXIAM: ISA EXtension for Integrated Accelerator Management. - Biagio Peccerillo; Elham Cheshmikhani; Mirco Mannino; Andrea Mondelli; Sandro Bartolini (IEEE Access, 2023)

Adaptive Dosing Control System Through ARIMA Model for Peristaltic Pumps. - Davide Privitera; Stefano Bellissima; Sandro Bartolini (IEEE Access, 2023)

Integration of RISC-V Page Table Walk in gem5 SE Mode. - Mirco Mannino; Yinting Huang; Biagio Peccerillo; Alessio Medaglini; Sandro Bartolini (RAPIDO@HiPEAC, 2024)

DeVAS: Decoupled Virtual Address Spaces. - Mirco Mannino; Biagio Peccerillo; Andrea Mondelli; Sandro Bartolini (SBAC-PAD, 2024)

High-Performance Multi-Object Tracking for Autonomous Driving in Urban Scenarios With Heterogeneous Embedded Boards. - Alessio Medaglini; Biagio Peccerillo; Sandro Bartolini (IEEE Access, 2025)

Ensemble Methods for Peristaltic Pump Accuracy Enhancement. - Davide Privitera; Alessandro Mecocci; Sandro Bartolini (IEEE Access, 2025)