A 32-bank 1 Gb self-strobing synchronous DRAM with 1 GByte/s bandwidth. - Jei-Hwan Yoo; Chang-Hyun Kim; Kyu-Chan Lee; Kye-Hyun Kyung; Seung-Moon Yoo; Jung-Hwa Lee; Moon-Hae Son; Jin-Man Han; Bok-Moon Kang; Ejaz Haq; Sang-Bo Lee; Jai-Hoon Sim; et al. (IEEE J. Solid State Circuits, 1996)

Low-voltage, high-speed circuit designs for gigabit DRAMs. - Kyu-Chan Lee; Changhyun Kim; Dong-Ryul Ryu; Jai-Hoon Sim; Sang-Bo Lee; Byung-Sik Moon; Keum-Yong Kim; Nam-Jong Kim; Seung-Moon Yoo; Hongil Yoon; Jei-Hwan Yoo; Soo-In Cho (IEEE J. Solid State Circuits, 1997)

A 64-Mbit, 640-MByte/s bidirectional data strobed, double-data-rate SDRAM with a 40-mW DLL for a 256-MByte memory system. - Chang-Hyun Kim; Jung-Hwa Lee; J. B. Lee; Beomsup Kim; C. S. Park; Sang-Bo Lee; S. Y. Lee; C. W. Park; J. G. Roh; Hyoung Sik Nam; D. Y. Kim; D. Y. Lee; et al. (IEEE J. Solid State Circuits, 1998)

A 1 Gbit synchronous dynamic random access memory with an independent subarray-controlled scheme and a hierarchical decoding scheme. - Kyu-Chan Lee; Changhyun Kim; Hongil Yoon; Keum-Yong Kim; Byung-Sik Moon; Sang-Bo Lee; Jung-Hwa Lee; Nam-Jong Kim; Soo-In Cho (IEEE J. Solid State Circuits, 1998)

A low-jitter mixed-mode DLL for high-speed DRAM applications. - Jae Joon Kim; Sang-Bo Lee; Tae-Sung Jung; Chang-Hyun Kim; Soo-In Cho; Beomsup Kim (IEEE J. Solid State Circuits, 2000)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. - Sang-Bo Lee; Seong-Jin Jang; Jin-Seok Kwak; Sang-Jun Hwang; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)