A high resolution metastability-independent two-step gated ring oscillator TDC with enhanced noise shaping. - Sang-Hye Chung; Kyu-Dong Hwang; Won-Young Lee; Lee-Sup Kim (ISCAS, 2010)

A 7.4 Gb/s forwarded clock receiver based on first-harmonic injection-locked oscillator using AC coupled clock multiplication unit in 0.13µm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (CICC, 2011)

Area-efficient dynamic thermal management unit using MDLL with shared DLL scheme for many-core processors. - Seungwook Paek; Jiehwan Oh; Sang-Hye Chung; Lee-Sup Kim (ISCAS, 2011)

1.22mW/Gb/s 9.6Gb/s data jitter mixing forwarded-clock receiver robust against power noise with 1.92ns latency mismatch between data and clock in 65nm CMOS. - Sang-Hye Chung; Lee-Sup Kim (VLSIC, 2012)

A Mobile 3-D Display Processor With A Bandwidth-Saving Subdivider. - Seok-Hoon Kim; Sung-Eui Yoon; Sang-Hye Chung; Young-Jun Kim 001; Hong-Yun Kim; Kyusik Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2012)

An 8Gb/s 0.65mW/Gb/s forwarded-clock receiver using an ILO with dual feedback loop and quadrature injection scheme. - Ji-Hwan Seol; Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Joo-Sun Choi; Lee-Sup Kim (ISSCC, 2013)

A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth. - Sang-Hye Chung; Young-Ju Kim 001; Kyung-Soo Ha; Seung-Jun Bae; Jung-Bae Lee; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A Quarter-Rate Forwarded Clock Receiver Based on ILO With Low Jitter Tracking Bandwidth Variation Using Phase Shifting Phenomenon in 65 nm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

A 9.6 Gb/s 0.96 mW/Gb/s Forwarded Clock Receiver With High Jitter Tolerance Using Mixing Cell Integrated Injection-Locked Oscillator. - Young-Ju Kim 001; Sang-Hye Chung; Kyung-Soo Ha; Seung-Jun Bae; Lee-Sup Kim (IEEE Trans. Circuits Syst. I Regul. Pap., 2015)

A 9.6-Gb/s 1.22-mW/Gb/s Data-Jitter Mixing Forwarded-Clock Receiver in 65-nm CMOS. - Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A Forwarded Clock Receiver Based on Injection-Locked Oscillator With AC-Coupled Clock Multiplication Unit in 0.13 µm CMOS. - Young-Ju Kim 001; Sang-Hye Chung; Lee-Sup Kim (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A 10-Gb/s 0.71-pJ/bit Forwarded-Clock Receiver Tolerant to High-Frequency Jitter in 65-nm CMOS. - Sang-Hye Chung; Young-Ju Kim 001; Yong-Hun Kim; Lee-Sup Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2016)