A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (A-SSCC, 2014)

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process. - Taeho Kim; Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Jiheon Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (A-SSCC, 2015)

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (VLSIC, 2015)

A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process. - Sang-Hyeok Chu; Woo-Rham Bae; Gyu-Seob Jeong; Sungchun Jang; Sungwoo Kim 001; Jiho Joo; Gyungock Kim; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2015)

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection. - Sungchun Jang; Sungwoo Kim 001; Sang-Hyeok Chu; Gyu-Seob Jeong; Yoonsoo Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2015)

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Gm Bias. - Gyu-Seob Jeong; Sang-Hyeok Chu; Yoonsoo Kim; Sungchun Jang; Sungwoo Kim 001; Woo-Rham Bae; Sung-Yong Cho; Haram Ju; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2016)

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel. - Kwanseo Park; Jinhyung Lee; Kwangho Lee; Min-Seong Choo; Sungchun Jang; Sang-Hyeok Chu; Sungwoo Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2017)

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS. - Jeongho Hwang; Gyu-Seob Jeong; Sang-Hyeok Chu; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (BCICTS, 2018)

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier. - Byoung-Joo Yoo; Dong-Hyuk Lim; Hyonguk Pang; June-Hee Lee; Seung-Yeob Baek 002; Naxin Kim; Dong-Ho Choi; Young-Ho Choi; Hyeyeon Yang; Taehun Yoon; Sang-Hyeok Chu; Kangjik Kim; et al. (ISSCC, 2020)

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS. - Jeongho Hwang; Sang-Hyeok Chu; Gyu-Seob Jeong; Yeojoon Youn; Wooseok Kim; Taeik Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)