A Case Study in Distributed Locking Protocol on Linux Clusters. - Sang-Jun Hwang; Jaechun No; Sung-Soon Park 001 (International Conference on Computational Science (1), 2005)

A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. - Sang-Bo Lee; Seong-Jin Jang; Jin-Seok Kwak; Sang-Jun Hwang; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)

A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays. - Aram Shin; Sang Jun Hwang; Seung Woo Yu; Man Young Sung (ISQED, 2007)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface. - Sang Joon Hwang; Young-Hyun Jun; Man Young Sung (IEICE Electron. Express, 2008)

Design of Organic TFT Pixel Electrode Circuit for Active-Matrix OLED Displays. - Aram Shin; Sang Jun Hwang; Seung Woo Yu; Man Young Sung (J. Comput., 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)

DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. - Seungki Hong; Dongha Kim; Jaehyung Lee; Reum Oh; Changsik Yoo; Sang Joon Hwang; Jooyoung Lee (CoRR, 2023)

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. - Changyoung Lee; Youngseok Park; Hyunchul Yoon; Seryeong Yoon; Donggeon Kim; Bokyeon Won; Junhwa Song; In-Jae Bae; Jaejoon Song; Kyuchang Kang; Jaehyuk Kim; Kyungrak Cho; et al. (A-SSCC, 2024)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)