A 12b 50 MHz 3.3V CMOS acquisition time minimized A/D converter. - Young-Deuk Jeon; Byeong-Lyeol Jeon; Seung-Chul Lee; Sang-Min Yoo; Seung-Hoon Lee 006 (ASP-DAC, 2000)

Acquisition-time minimization and merged-capacitor switching techniques for sampling-rate and resolution improvement of CMOS ADCs. - Young-Deuk Jeon; Seung-Chul Lee; Sang-Min Yoo; Seung-Hoon Lee 006 (ISCAS, 2000)

A 2.5 V 10 b 120 MSample/s CMOS pipelined ADC with high SFDR. - Sang-Min Yoo; Tae-Hwan Oh; Jung-Woong Moon; Seung-Hoon Lee 006; Un-Ku Moon (CICC, 2002)

A 10-b 150-MSample/s 1.8-V 123-mW CMOS A/D converter with 400-MHz input bandwidth. - Jong-Bum Park; Sang-Min Yoo; Se-Won Kim; Young-Jae Cho; Seung-Hoon Lee 006 (IEEE J. Solid State Circuits, 2004)

A 2.5-V 10-b 120-MSample/s CMOS pipelined ADC based on merged-capacitor switching. - Sang-Min Yoo; Jong-Bum Park; Seung-Hoon Lee 006; Un-Ku Moon (IEEE Trans. Circuits Syst. II Express Briefs, 2004)

A 3.0 V 72mW 10b 100 MSample/s Nyquist-rate CMOS pipelined ADC in 0.54 mm2. - Tae-Hwan Oh; Sang-Min Yoo; Kyoung-Ho Moon; Jae-Whui Kim (ISCAS, 2006)

A 3.0V 12b 120 Msample/s CMOS pipelined ADC. - Sang-Min Yoo; Tae-Hwan Oh; Ho-Young Lee; Kyung-Ho Moon; Jae-Whui Kim (ISCAS, 2006)

A 15mW 0.2mm2 50MS/s ADC with wide input range. - Hee-Cheol Choi; Ju-Wha Kim; Sang-Min Yoo; Kang-Jin Lee; Tae-Hwan Oh; Mi-Jung Seo; Jae-Whui Kim (ISSCC, 2006)

Towards greener wireless transmission: Efficient power amplifier design. - Karthik Natarajan; Sang-Min Yoo; David J. Allstot; Jeffrey S. Walling (IGCC, 2011)

A switched-capacitor power amplifier for EER/polar transmitters. - Sang-Min Yoo; Jeffrey S. Walling; Eum Chan Woo; David J. Allstot (ISSCC, 2011)

A Switched-Capacitor RF Power Amplifier. - Sang-Min Yoo; Jeffrey S. Walling; Eum Chan Woo; Benjamin Jann; David J. Allstot (IEEE J. Solid State Circuits, 2011)

Digital power amplifier: A new way to exploit the switched-capacitor circuit. - Jeffrey S. Walling; Sang-Min Yoo; David J. Allstot (IEEE Commun. Mag., 2012)

A Class-G Switched-Capacitor RF Power Amplifier. - Sang-Min Yoo; Jeffrey S. Walling; Ofir Degani; Benjamin Jann; Ram Sadhwani; Jacques Christophe Rudell; David J. Allstot (IEEE J. Solid State Circuits, 2013)

A Watt-Level Quadrature Class-G Switched-Capacitor Power Amplifier With Linearization Techniques. - Si-Wook Yoo; Shih-Chang Hung; Sang-Min Yoo (IEEE J. Solid State Circuits, 2019)

10.7 A 0.26mm2 DPD-Less Quadrature Digital Transmitter With 30dB Pout Range in 65nm CMOS. - Si-Wook Yoo; Shih-Chang Hung; Jeffrey S. Walling; David J. Allstot; Sang-Min Yoo (ISSCC, 2020)

24.4 A Watt-Level Multimode Multi-Efficiency-Peak Digital Polar Power Amplifier with Linear Single-Supply Class-G Technique. - Si-Wook Yoo; Shih-Chang Hung; Sang-Min Yoo (ISSCC, 2020)

A Multimode Multi-Efficiency-Peak Digital Power Amplifier. - Si-Wook Yoo; Shih-Chang Hung; Sang-Min Yoo (IEEE J. Solid State Circuits, 2020)

A Quadrature Class-G Complex-Domain Doherty Digital Power Amplifier. - Shih-Chang Hung; Si-Wook Yoo; Sang-Min Yoo (IEEE J. Solid State Circuits, 2021)

A Temperature Compensated Ring Oscillator With LC-Based Period Error Detection. - Seongun Bae; Minseob Lee; Sang-Min Yoo; Jae-Yoon Sim (IEEE Trans. Very Large Scale Integr. Syst., 2023)