A design of the new FPGA with data path logic and run time block reconfiguration method. - Jaeyoung Kwak; Sang-Sic Yoon; Hung-Jun Kwon; Kwyro Lee (ISCAS (1), 1999)

Implementation of a parallel turbo decoder with dividable interleaver. - Jaeyoung Kwak; Sook Min Park; Sang-Sic Yoon; Kwyro Lee (ISCAS (2), 2003)

A 16Gb/s/pin 8Gb GDDR6 DRAM with bandwidth extension techniques for high-speed applications. - Kyu-Dong Hwang; Boram Kim; Sang-Yeon Byeon; Kyu-Young Kim; Dae-Han Kwon; Hyun-Bae Lee; Geun-Il Lee; Sang-Sic Yoon; Jin-Youp Cha; Soo-Young Jang; Seung-Hun Lee; Yongsuk Joo; et al. (ISSCC, 2018)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)