A 4Gb/s adaptive FFE/DFE receiver with data-dependent jitter measurement. - Tae-Ho Kim; Jong-Seok Han; Sang-Soon Im; Jae-Young Jang; Jin-Ku Kang (ESSCIRC, 2011)

A 1.62/2.7/5.4Gbps clock and data recovery circuit for DisplayPort 1.2. - Jin-Cheol Seo; Sang-Soon Im; Kwan-Hee Yoon; Seung-Wook Oh; Taek-Joon An; Gi-Yeol Bae; Jin-Ku Kang (SoCC, 2012)

A low jitter clock and data recovery with a single edge sensing Bang-Bang PD. - Taek-Joon Ahn; Sang-Soon Im; Yong-Sung Ahn; Jin-Ku Kang (IEICE Electron. Express, 2014)