High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data Widths. - Sang-uhn Cha; Hongil Yoon (ISCAS, 2007)

Self-correcting check bit generator of error correction codes for memories. - Sang-uhn Cha; Hongil Yoon (IEICE Electron. Express, 2013)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang; Kwang-Il Park; Seong-Jin Jang; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

A 16Gb LPDDR4X SDRAM with an NBTI-tolerant circuit solution, an SWD PMOS GIDL reduction technique, an adaptive gear-down scheme and a metastable-free DQS aligner in a 10nm class DRAM process. - Ki Chul Chun; Yonggyu Chu; Jin-Seok Heo; Tae-Sung Kim; Soohwan Kim; Hui-Kap Yang; Mi-Jo Kim; Chang-Kyo Lee; Ju-Hwan Kim; Hyunchul Yoon; Chang-Ho Shin; Sang-uhn Cha; et al. (ISSCC, 2018)

22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme. - Chi-Sung Oh; Ki Chul Chun; Young-Yong Byun; Yong-Ki Kim; So-Young Kim; Yesin Ryu; Jaewon Park; Sinho Kim; Sang-uhn Cha; Dong-Hak Shin; Jungyu Lee 002; Jong-Pil Son; et al. (ISSCC, 2020)