A Dynamically Biased Multiband 2G/3G/4G Cellular Transmitter in 28 nm CMOS. - Siddharth Seth; Dae Hyun Kwon; Sriramkumar Venugopalan; Sang Won Son; Yongrong Zuo; Venumadhav Bhagavatula; Jaehyun Lim; Dongjin Oh; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2016)

13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOS. - Venumadhav Bhagavatula; Dae Hyun Kwon; Jaehun Lee; Quang-Diep Bui; Jeong-Hyun Choi; Siuchuang-Ivan Lu; Sang Won Son (ISSCC, 2017)

24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICs. - Chih-Wei Yao; Wing Fai Loke; Ronghua Ni; Yongping Han; Haoyang Li; Kunal Godbole; Yongrong Zuo; Sangsoo Ko; Nam-Seog Kim 001; Sangwook Han; Ikkyun Jo; Joonhee Lee; et al. (ISSCC, 2017)

A 14-nm 0.14-psrms Fractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration. - Chih-Wei Yao; Ronghua Ni; Chung Lau; Wanghua Wu; Kunal Godbole; Yongrong Zuo; Sangsoo Ko; Nam-Seog Kim 001; Sangwook Han; Ikkyun Jo; Joonhee Lee; Juyoung Han; et al. (IEEE J. Solid State Circuits, 2017)

A 28-nm 75-fsrms Analog Fractional- $N$ Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle Correction. - Wanghua Wu; Chih-Wei Yao; Kunal Godbole; Ronghua Ni; Pei-Yuan Chiang; Yongping Han; Yongrong Zuo; Ashutosh Verma; Ivan Siu-Chuang Lu; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2019)

32.2 A 14nm Analog Sampling Fractional-N PLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 80fs Integrated Jitter and 93fs at Near-Integer Channels. - Wanghua Wu; Chih-Wei Yao; Chengkai Guo; Pei-Yuan Chiang; Pak-Kim Lau; Lei Chen; Sang Won Son; Thomas Byunghak Cho (ISSCC, 2021)

A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO. - Wanghua Wu; Chih-Wei Yao; Chengkai Guo; Pei-Yuan Chiang; Lei Chen; Pak-Kim Lau; Zhanjun Bai; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2021)

A 16-Channel, 28/39GHz Dual-Polarized 5G FR2 Phased-Array Transceiver IC with a Quad-Stream IF Transceiver Supporting Non-Contiguous Carrier Aggregation up to 1.6GHz BW. - Ashutosh Verma; Venumadhav Bhagavatula; Amitoj Singh; Wanghua Wu; Hariharan Nagarajan; Pak-Kim Lau; Xiaohua Yu; Omar Elsayed; Ajaypat Jain; Anirban Sarkar 002; Fan Zhang; Che-Chun Kuo; et al. (ISSCC, 2022)

A 5G FR2 Power-Amplifier With an Integrated Power-Detector for Closed-Loop EIRP Control. - Venumadhav Bhagavatula; Fan Zhang; Che-Chun Kuo; Anirban Sarkar 002; Ashutosh Verma; Tienyu Chang; Xiaohua Yu; Daeyoung Yoon; Ivan Siu-Chuang Lu; Sang Won Son; Thomas Byunghak Cho (IEEE J. Solid State Circuits, 2022)

Semi-supervsied Learning-based Sound Event Detection using Freuqency Dynamic Convolution with Large Kernel Attention for DCASE Challenge 2023 Task 4. - Ji Won Kim; Sang Won Son; Yoonah Song; Hong Kook Kim; Il Hoon Song; Jeong Eun Lim (CoRR, 2023)

Sound event detection based on auxiliary decoder and maximum probability aggregation for DCASE Challenge 2024 Task 4. - Sang Won Son; Jongyeon Park; Hong Kook Kim; Sulaiman Vesal; Jeong Eun Lim (CoRR, 2024)