11-Bit 1.8uW 40KS/s segmented SAR ADC for sensor applications. - Behnam Samadpoor Rikan; Sang-Yun Kim 001; Kang-Yoon Lee (ISOCC, 2016)

An Ultra Low Power, 3-Wire Serial Interface Design for Data Converters in Pin-Constrainted Applications with 180 nm CMOS Technology. - Imran Ali; Muhammad Riaz ur Rehman; Sang-Yun Kim 001; Nabeel Ahmad; Kang-Yoon Lee (FIT, 2017)

A 10-bit 1 MS/s segmented Dual-Sampling SAR ADC with reduced switching energy. - Behnam Samadpoor Rikan; Hamed Abbasizadeh; Young-Jun Park 005; Hye-Yeong Kang; SangYun Kim 001; YoungGun Pu; Minjae Lee 001; Keum-Cheol Hwang; Youngoo Yang; Kang-Yoon Lee (Microelectron. J., 2017)

An Inductive 2-D Position Detection IC With 99.8% Accuracy for Automotive EMR Gear Control System. - SangYun Kim 001; Hamed Abbasizadeh; Imran Ali; HongJin Kim; SungHun Cho; YoungGun Pu; Sang-Sun Yoo; Minjae Lee 001; Keum-Cheol Hwang; Youngoo Yang; Kang-Yoon Lee (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A 5.2 GHz RF Energy Harvester System Using Reconfigurable Parallel Rectenna. - Hamed Abbasizadeh; Sang Yun Kim 001; Truong Thi Kim Nga; Danial Khan; SeongJin Oh; Sung Jin Kim; Kwan-Tae Kim; Dong In Kim; Kang-Yoon Lee (MWSCAS, 2018)

A 6-bit 4 MS/s 26fJ/conversion-step segmented SAR ADC with reduced switching energy for BLE. - Behnam Samadpoor Rikan; Hamed Abbasizadeh; SungHun Cho; Sang-Yun Kim 001; Imran Ali; Sung-Jin Kim; Dong-Soo Lee; YoungGun Pu; Minjae Lee 001; Keum-Cheol Hwang; Youngoo Yang; Kang-Yoon Lee (Int. J. Circuit Theory Appl., 2018)

A High Noise Immunity, 28 × 16-Channel Finger Touch Sensing IC Using OFDM and Frequency Translation Technique. - SangYun Kim 001; Behnam Samadpoor Rikan; YoungGun Pu; Sang-Sun Yoo; Minjae Lee 001; Keum-Cheol Hwang; Youngoo Yang; Kang-Yoon Lee (Sensors, 2018)

A Sigma-Delta ADC for Signal Conditioning IC of Automotive Piezo-Resistive Pressure Sensors with over 80 dB SNR. - Behnam Samadpoor Rikan; Sang-Yun Kim 001; Nabeel Ahmad; Hamed Abbasizadeh; Muhammad Riaz ur Rehman; Khuram Shehzad; Arash Hejazi; Reza E. Rad; Deeksha Verma; Kang-Yoon Lee (Sensors, 2018)

A 0.33-1 GHz Open-Loop Duty Cycle Corrector With Digital Falling Edge Modulator. - Kyung-Tae Kang; Sang-Yun Kim 001; Sung Jin Kim; Dong-Soo Lee; Sang-Sun Yoo; Kang-Yoon Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A 39.5-dB SNR, 300-Hz Frame-Rate, 56 × 70-Channel Read-Out IC for Electromagnetic Resonance Touch Panels. - SangYun Kim 001; SungHun Cho; YoungGun Pu; Sang-Sun Yoo; Minjae Lee 001; Keum-Cheol Hwang; Youngoo Yang; Kang-Yoon Lee (IEEE Trans. Ind. Electron., 2018)

A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power. - Kyung-Soo Ha; Chang-Kyo Lee; Dongkeon Lee; Daesik Moon; Jin-Hun Jang; Hyong-Ryol Hwang; Hyung-Joon Chi; Junghwan Park; Seungjun Shin; Dukha Park; Sang-Yun Kim 001; Sukhyun Lim; et al. (ISSCC, 2019)

Design of a 900 MHz Dual-Mode SWIPT for Low-Power IoT Devices. - Hamed Abbasizadeh; Sang Yun Kim 001; Behnam Samadpoor Rikan; Arash Hejazi; Danial Khan; YoungGun Pu; Keum-Cheol Hwang; Youngoo Yang; Dong In Kim; Kang-Yoon Lee (Sensors, 2019)

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process. - Hyung-Joon Chi; Chang-Kyo Lee; Junghwan Park; Jin-Seok Heo; Jaehoon Jung; Dongkeon Lee; Dae-Hyun Kim 003; Dukha Park; Kihan Kim; Sang-Yun Kim 001; Jinsol Park; Hyunyoon Cho; et al. (ISSCC, 2020)

An 8.5-Gb/s/Pin 12-Gb LPDDR5 SDRAM With a Hybrid-Bank Architecture, Low Power, and Speed-Boosting Techniques. - Chang-Kyo Lee; Hyung-Joon Chi; Jin-Seok Heo; Junghwan Park; Jin-Hun Jang; Dongkeon Lee; Jaehoon Jung; Dong-Hun Lee; Dae-Hyun Kim 003; Kihan Kim; Sang-Yun Kim 001; Dukha Park; et al. (IEEE J. Solid State Circuits, 2021)