25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A 16Gb 1.2V 3.2Gb/s/pin DDR4 SDRAM with improved power distribution and repair strategy. - Seokbo Shim; Sungho Kim; Jooyoung Bae; Keunsik Ko; Eunryeong Lee; Kwidong Kim; Kyeongtae Kim; Sangho Lee; Jinhoon Hyun; Insung Koh; Joonhong Park; Minjeong Kim; et al. (ISSCC, 2018)