Hierarchical representation of digitized curves through dominant point detection. - Biswajit Sarkar; Sanghamitra Roy; Debranjan Sarkar (Pattern Recognit. Lett., 2003)

An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. - Sanghamitra Roy; Prithviraj Banerjee (DAC, 2004)

An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. - Sanghamitra Roy; Debjit Sinha; Prithviraj Banerjee (FPGA, 2004)

ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. - Sanghamitra Roy; Weijen Chen (ICCAD, 2005)

An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. - Sanghamitra Roy; Prith Banerjee (IEEE Trans. Computers, 2005)

ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. - Sanghamitra Roy; Charlie Chung-Ping Chen (ISQED, 2006)

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. - Sanghamitra Roy; Charlie Chung-Ping Chen (ASP-DAC, 2007)

Numerically Convex Forms and Their Application in Gate Sizing. - Sanghamitra Roy; Weijen Chen; Charlie Chung-Ping Chen; Yu Hen Hu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

An optimal algorithm for sizing sequential circuits for industrial library based designs. - Sanghamitra Roy; Yu Hen Hu; Charlie Chung-Ping Chen; Shih-Pin Hung; Tse-Yu Chiang; Jiuan-Guei Tseng (ASP-DAC, 2008)

Wire Sizing. - Sanghamitra Roy; Charlie Chung-Ping Chen (Handbook of Algorithms for Physical Design Automation, 2008)

Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. - Sanghamitra Roy; Koushik Chakraborty (ICCD, 2010)

A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures. - Sanghamitra Roy; Koushik Chakraborty (ISQED, 2010)

Rethinking Threshold Voltage Assignment in 3D Multicore Designs. - Koushik Chakraborty; Sanghamitra Roy (VLSI Design, 2010)

A Novel Threshold Voltage Assignment for 3D Multicore Designs. - Koushik Chakraborty; Sanghamitra Roy (J. Low Power Electron., 2010)

Topologically homogeneous power-performance heterogeneous multicore systems. - Koushik Chakraborty; Sanghamitra Roy (DATE, 2011)

Exploring high throughput computing paradigm for global routing. - Yiding Han; Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (ICCAD, 2011)

Optimizing simulated annealing on GPU: A case study with IC floorplanning. - Yiding Han; Sanghamitra Roy; Koushik Chakraborty (ISQED, 2011)

Analysis and mitigation of NBTI aging in register file: An end-to-end approach. - Saurabh Kothawade; Koushik Chakraborty; Sanghamitra Roy (ISQED, 2011)

Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. - Mandar Padmawar; Sanghamitra Roy; Koushik Chakraborty (ISQED, 2011)

A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. - Yiding Han; Koushik Chakraborty; Sanghamitra Roy; Vilasita Kuntamukkala (VLSI Design, 2011)

Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. - Mandar Padmawar; Sanghamitra Roy; Koushik Chakraborty (J. Low Power Electron., 2011)

Exploiting dynamic micro-architecture usage in gate sizing. - Sanghamitra Roy; Koushik Chakraborty (Microprocess. Microsystems, 2011)

Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. - Yiding Han; Koushik Chakraborty; Sanghamitra Roy; Vilasita Kuntamukkala (ACM Trans. Design Autom. Electr. Syst., 2011)

Towards graceful aging degradation in NoCs through an adaptive routing algorithm. - Kshitij Bhardwaj; Koushik Chakraborty; Sanghamitra Roy (DAC, 2012)

Predicting timing violations through instruction-level path sensitization analysis. - Sanghamitra Roy; Koushik Chakraborty (DAC, 2012)

An MILP-based aging-aware routing algorithm for NoCs. - Kshitij Bhardwaj; Koushik Chakraborty; Sanghamitra Roy (DATE, 2012)

DOC: Fast and accurate congestion analysis for global routing. - Yiding Han; Koushik Chakraborty; Sanghamitra Roy (ICCD, 2012)

Mitigating NBTI in the physical register file through stress prediction. - Saurabh Kothawade; Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (ICCD, 2012)

Designing for dark silicon: a methodological perspective on energy efficient systems. - Jason M. Allred; Sanghamitra Roy; Koushik Chakraborty (ISLPED, 2012)

Power-Performance Yield optimization for MPSoCs using MILP. - Kshitij Bhardwaj; Sanghamitra Roy; Koushik Chakraborty (ISQED, 2012)

Process variation aware DRAM design using block based adaptive body biasing algorithm. - Satyajit Desai; Sanghamitra Roy; Koushik Chakraborty (ISQED, 2012)

Analysis of intermittent timing fault vulnerability. - Saurabh Kothawade; Koushik Chakraborty; Sanghamitra Roy; Yiding Han (Microelectron. Reliab., 2012)

Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. - Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Very Large Scale Integr. Syst., 2012)

DMR3D: dynamic memory relocation in 3D multicore systems. - Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (DAC, 2013)

HCI-tolerant NoC router microarchitecture. - Dean Michael Ancajas; James McCabe Nickerson; Koushik Chakraborty; Sanghamitra Roy (DAC, 2013)

Efficiently tolerating timing violations in pipelined microprocessors. - Koushik Chakraborty; Brennan Cozzens; Sanghamitra Roy; Dean Michael Ancajas (DAC, 2013)

Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach. - Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (DATE, 2013)

Long term sustainability of differentially reliable systems in the dark silicon era. - Jason M. Allred; Sanghamitra Roy; Koushik Chakraborty (ICCD, 2013)

A global router on GPU architecture. - Yiding Han; Koushik Chakraborty; Sanghamitra Roy (ICCD, 2013)

Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design. - Satyajit Desai; Sanghamitra Roy (J. Low Power Electron., 2013)

Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems. - Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Tackling QoS-induced aging in exascale systems through agile path selection. - Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy; Jason M. Allred (CODES+ISSS, 2014)

Fort-NoCs: Mitigating the Threat of a Compromised NoC. - Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (DAC, 2014)

DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors. - Hu Chen; Sanghamitra Roy; Koushik Chakraborty (DATE, 2014)

Exploiting static and dynamic locality of timing errors in robust L1 cache design. - Hu Chen; Sanghamitra Roy; Koushik Chakraborty (ISQED, 2014)

Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight. - Jason M. Allred; Sanghamitra Roy; Koushik Chakraborty (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks. - Hu Chen; Dieudonne Manzi; Sanghamitra Roy; Koushik Chakraborty (DAC, 2015)

Tackling voltage emergencies in NoC through timing error resilience. - Rajesh Jayashankara Shridevi; Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (ISLPED, 2015)

Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip. - Rajesh J. S.; Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (NOCS, 2015)

Resilient Cache Design for Mobile Processors in the Near-Threshold Regime. - Dieudonne Manzi Mugisha; Hu Chen; Sanghamitra Roy; Koushik Chakraborty (J. Low Power Electron., 2015)

DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors. - Hu Chen; Sanghamitra Roy; Koushik Chakraborty (ACM Trans. Design Autom. Electr. Syst., 2015)

Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm. - Dean Michael Ancajas; Kshitij Bhardwaj; Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Very Large Scale Integr. Syst., 2015)

SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost. - Prabal Basu; Hu Chen; Shamik Saha; Koushik Chakraborty; Sanghamitra Roy (DAC, 2016)

Catching the flu: emerging threats from a third party power management unit. - Rajesh Jayashankara Shridevi; Chidhambaranathan Rajamanikkam; Koushik Chakraborty; Sanghamitra Roy (DAC, 2016)

Synergistic timing speculation for multi-threaded programs. - Atif Yasin; Jeff Jun Zhang; Hu Chen; Siddharth Garg; Sanghamitra Roy; Koushik Chakraborty (DAC, 2016)

PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms. - Prabal Basu; Rajesh Jayashankara Shridevi; Koushik Chakraborty; Sanghamitra Roy (DATE, 2016)

BoostNoC: power efficient network-on-chip architecture for near threshold computing. - Chidhambaranathan Rajamanikkam; Rajesh J. S.; Koushik Chakraborty; Sanghamitra Roy (ICCAD, 2016)

Revamping timing error resilience to tackle choke points at NTC systems. - Aatreyi Bal; Shamik Saha; Sanghamitra Roy; Koushik Chakraborty (DATE, 2017)

Security Measures Against a Rogue Network-on-Chip. - Rajesh Jayashankara Shridevi; Dean Michael Ancajas; Koushik Chakraborty; Sanghamitra Roy (J. Hardw. Syst. Secur., 2017)

Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit. - Asmita Pal; Aatreyi Bal; Koushik Chakraborty; Sanghamitra Roy (J. Low Power Electron., 2017)

SSAGA: SMs Synthesized for Asymmetric GPGPU Applications. - Shamik Saha; Prabal Basu; Chidhambaranathan Rajamanikkam; Aatreyi Bal; Koushik Chakraborty; Sanghamitra Roy (ACM Trans. Design Autom. Electr. Syst., 2017)

IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms. - Prabal Basu; Rajesh Jayashankara Shridevi; Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Trident: A comprehensive timing error resilient technique against choke points at NTC. - Aatreyi Bal; Sanghamitra Roy; Koushik Chakraborty (DATE, 2018)

Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC. - Pramesh Pandey; Asmita Pal; Koushik Chakraborty; Sanghamitra Roy (ISLPED, 2018)

ACE-GPU: Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU. - Tahmoures Shabanian; Aatreyi Bal; Prabal Basu; Koushik Chakraborty; Sanghamitra Roy (ISLPED, 2018)

FIFA: Exploring a Focally Induced Fault Attack Strategy in Near-Threshold Computing. - Prabal Basu; Chidhambaranathan Rajamanikkam; Aatreyi Bal; Pramesh Pandey; Trevor Carter; Koushik Chakraborty; Sanghamitra Roy (IEEE Embed. Syst. Lett., 2018)

TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans. - Chidhambaranathan Rajamanikkam; Kurt Brenning; Andrew Deakin; Sanghamitra Roy; Koushik Chakraborty (Microprocess. Microsystems, 2018)

Trident: Comprehensive Choke Error Mitigation in NTC Systems. - Aatreyi Bal; Sanghamitra Roy; Koushik Chakraborty (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Dynamic Choke Sensing for Timing Error Resilience in NTC Systems. - Aatreyi Bal; Shamik Saha; Sanghamitra Roy; Koushik Chakraborty (IEEE Trans. Very Large Scale Integr. Syst., 2018)

GreenTPU: Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit. - Pramesh Pandey; Prabal Basu; Koushik Chakraborty; Sanghamitra Roy (DAC, 2019)

Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis. - Sourav Sanyal; Prabal Basu; Aatreyi Bal; Sanghamitra Roy; Koushik Chakraborty (DATE, 2019)

Probabilistic Verification for Reliable Network-on-Chip System Design. - Benjamin Lewis; Arnd Hartmanns; Prabal Basu; Rajesh Jayashankara Shridevi; Koushik Chakraborty; Sanghamitra Roy; Zhen Zhang 006 (FMICS, 2019)

Securing Data Center Against Power Attacks. - Rajesh J. S.; Chidhambaranathan Rajamanikkam; Koushik Chakraborty; Sanghamitra Roy (J. Hardw. Syst. Secur., 2019)

Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System. - Chidhambaranathan Rajamanikkam; Rajesh J. S.; Koushik Chakraborty; Sanghamitra Roy (J. Low Power Electron., 2019)

EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit. - Noel Daniel Gundi; Tahmoures Shabanian; Prabal Basu; Pramesh Pandey; Sanghamitra Roy; Koushik Chakraborty; Zhen Zhang 006 (ASP-DAC, 2020)

TITAN: Uncovering the Paradigm Shift in Security Vulnerability at Near-Threshold Computing. - Prabal Basu; Pramesh Pandey; Aatreyi Bal; Chidhambaranathan Rajamanikkam; Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Emerg. Top. Comput., 2020)

GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit. - Pramesh Pandey; Prabal Basu; Koushik Chakraborty; Sanghamitra Roy (IEEE Trans. Very Large Scale Integr. Syst., 2020)

Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis. - Sourav Sanyal; Prabal Basu; Aatreyi Bal; Sanghamitra Roy; Koushik Chakraborty (IEEE Trans. Very Large Scale Integr. Syst., 2020)

UPTPU: Improving Energy Efficiency of a Tensor Processing Unit through Underutilization Based Power-Gating. - Pramesh Pandey; Noel Daniel Gundi; Koushik Chakraborty; Sanghamitra Roy (DAC, 2021)

Probabilistic Verification for Reliability of a Two-by-Two Network-on-Chip System. - Riley Roberts; Benjamin Lewis; Arnd Hartmanns; Prabal Basu; Sanghamitra Roy; Koushik Chakraborty; Zhen Zhang 006 (FMICS, 2021)

Voltage Scaling for Partitioned Systolic Array in A Reconfigurable Platform. - Rourab Paul; Sreetama Sarkar; Suman Sau; Koushik Chakraborty; Sanghamitra Roy; Amlan Chakrabarti (CoRR, 2021)

Understanding Security Threats in Emerging Neuromorphic Computing Architecture. - Chidhambaranathan Rajamanikkam; Rajesh J. S.; Sanghamitra Roy; Koushik Chakraborty (J. Hardw. Syst. Secur., 2021)

EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units. - Noel Daniel Gundi; Tahmoures Shabanian; Prabal Basu; Pramesh Pandey; Sanghamitra Roy; Koushik Chakraborty (IEEE Trans. Very Large Scale Integr. Syst., 2021)

STRIVE: Enabling Choke Point Detection and Timing Error Resilience in a Low-Power Tensor Processing Unit. - Noel Daniel Gundi; Zinnia Muntaha Mowri; Andrew Chamberlin; Sanghamitra Roy; Koushik Chakraborty (DAC, 2023)

STRIVE: Empowering a Low Power Tensor Processing Unit with Fault Detection and Error Resilience. - Noel Daniel Gundi; Sanghamitra Roy; Koushik Chakraborty (ACM Trans. Design Autom. Electr. Syst., 2025)