A3: Accelerating Attention Mechanisms in Neural Networks with Approximation. - Tae Jun Ham; Sungjun Jung; Seonghak Kim; Young H. Oh; Yeonhong Park; Yoonho Song; Jung-Hun Park; Sanghee Lee 002; Kyoung Park; Jae W. Lee; Deog-Kyoon Jeong (HPCA, 2020)

A 6b 48-GS/s Asynchronous 2b/cycle Time-Interleaved ADC in 28-nm CMOS. - Hong-Seok Choi; Seungha Roh; Sanghee Lee 002; Jung-Hoon Park; Kwanghoon Lee; Young-Ha Hwang; Deog-Kyoon Jeong (ISOCC, 2021)

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. - Jung-Hun Park; Kwang-Hoon Lee; Yongjae Lee; Jung-Woo Sull; Yoonho Song; Sanghee Lee 002; Hyeonseok Lee; Hoyeon Cho; Jonghyun Oh; Han-Gon Ko; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

A 2.5-32 Gb/s Gen 5-PCIe Receiver With Multi-Rate CDR Engine and Hybrid DFE. - Moon-Chul Choi; Sanghee Lee 002; Seungha Roh; Kwangho Lee; Jonghyun Oh; Sungwoo Kim 001; Kwandong Kim; Woo-Seok Choi; Jaeha Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. - Jung-Hun Park; Hyeonseok Lee; Hoyeon Cho; Sanghee Lee 002; Kwang-Hoon Lee; Han-Gon Ko; Deog-Kyoon Jeong (ISSCC, 2023)

An 8-GHz Octa-Phase Clock Corrector with Phase and Duty-Cycle Correction in 40-nm CMOS. - Jung-Woo Sull; Minkyo Shim; Jung-Hun Park; Sanghee Lee 002; Deog-Kyoon Jeong (MWSCAS, 2023)

A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS. - Sanghee Lee 002; Byungjun Kang; Woogeun Rhee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 3ns Idle-Exit Latency 0.28-28Gb/s/pin Single-Ended NRZ Die-to-Die Interface with Energy-Efficient Receiver and Background Noise Compensation. - Hyun-Seok Choi; Sunki Cho; Sanghee Lee 002; Hyeri Roh; Jeongeun Song; Honggyoo Ahn; Jihee Kim; Minchang Kim; Hankyu Chi; Deog-Kyoon Jeong; Woo-Seok Choi (CICC, 2025)