Timing Failure Analysis of Commercial CPUs Under Operating Stress. - Sanghoan Chang; Gwan Choi (DFT, 2006)

Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. - Sanghoan Chang; Gwan Choi (VLSI Design, 2007)

A 20nm 1.8V 8Gb PRAM with 40MB/s program bandwidth. - Youngdon Choi; Ickhyun Song; Mu-Hui Park; Hoeju Chung; Sanghoan Chang; Beakhyoung Cho; Jinyoung Kim; Younghoon Oh; Dukmin Kwon; Jung Sunwoo; Junho Shin; Yoohwan Rho; et al. (ISSCC, 2012)

The solid-state drive technology, today and tomorrow. - Sangyeun Cho; Sanghoan Chang; Insoon Jo (ICDE, 2015)