Fast Localization Algorithm for The Cleaning Robot By Using Self-Organization Map. - Sanghoon Baek; Suyong Ahn; Se-Young Oh (CIRA, 2007)

Online complete coverage path planning for mobile robots based on linked spiral paths using constrained inverse distance transform. - Young-Ho Choi; Tae-Kyeong Lee; Sanghoon Baek; Se-Young Oh (IROS, 2009)

Generating topological map from occupancy grid-map using virtual door detection. - Kwangro Joo; Tae-Kyeong Lee; Sanghoon Baek; Se-Young Oh (IEEE Congress on Evolutionary Computation, 2010)

Experimental Results of Single Carrier Digital Modulation for Underwater Sensor Networks. - Se-Young Kim; Jeong-Woo Han; Ki-Man Kim; Sanghoon Baek; Hyungchul Kim; Changhwa Kim (EUC, 2010)

Complete coverage algorithm based on linked smooth spiral paths for mobile robots. - Tae-Kyeong Lee; Sanghoon Baek; Se-Young Oh; Young-Ho Choi (ICARCV, 2010)

Integrated On-Line Localization, Mapping and Coverage Algorithm of Unknown Environments for Robotic Vacuum Cleaners Based on Minimal Sensing. - Sanghoon Baek; Tae-Kyeong Lee; Se-Young Oh; Kwangro Ju (Adv. Robotics, 2011)

Smooth coverage path planning and control of mobile robots based on high-resolution grid map representation. - Tae-Kyeong Lee; Sanghoon Baek; Young-Ho Choi; Se-Young Oh (Robotics Auton. Syst., 2011)

Sector-based maximal online coverage of unknown environments for cleaning robots with limited sensing. - Tae-Kyeong Lee; Sanghoon Baek; Se-Young Oh (Robotics Auton. Syst., 2011)

13.2 A 14nm FinFET 128Mb 6T SRAM with VMIN-enhancement techniques for low-power applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2014)

A 14 nm FinFET 128 Mb SRAM With VMIN Enhancement Techniques for Low-Power Applications. - Taejoong Song; Woojin Rim; Jonghoon Jung; Giyong Yang; Jaeho Park; Sunghyun Park 003; Yongho Kim; Kang-Hyun Baek; Sanghoon Baek; Sang-Kyu Oh; Jinsuk Jung; Sungbong Kim; et al. (IEEE J. Solid State Circuits, 2015)

17.1 A 10nm FinFET 128Mb SRAM with assist adjustment system for power, performance, and area optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Jonghoon Jung; Giyong Yang; Sanghoon Baek; Jaeseung Choi 001; Bongjae Kwon; Yunwoo Lee; Sungbong Kim; Gyu-Hong Kim; et al. (ISSCC, 2016)

12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysis. - Taejoong Song; Hoonki Kim; Woojin Rim; Yongho Kim; Sunghyun Park 003; Changnam Park; Minsun Hong; Giyong Yang; Jeongho Do; Jinyoung Lim; Seungyoung Lee; Ingyum Kim; et al. (ISSCC, 2017)

A 10 nm FinFET 128 Mb SRAM With Assist Adjustment System for Power, Performance, and Area Optimization. - Taejoong Song; Woojin Rim; Sunghyun Park 003; Yongho Kim; Giyong Yang; Hoonki Kim; Sanghoon Baek; Jonghoon Jung; Bongjae Kwon; Sungwee Cho; Hyuntaek Jung; Yongjae Choo; et al. (IEEE J. Solid State Circuits, 2017)

24.3 A 3nm Gate-All-Around SRAM Featuring an Adaptive Dual-BL and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Woojin Rim; Hoonki Kim; Keun Hwi Cho; Taeyeong Kim; Taejung Lee; Geumjong Bae; Dong-Won Kim; S. D. Kwon; Sanghoon Baek; Jonghoon Jung; Jongwook Kye; et al. (ISSCC, 2021)

3nm Gate-All-Around (GAA) Design-Technology Co-Optimization (DTCO) for succeeding PPA by Technology. - Taejoong Song; Hakchul Jung; Giyoung Yang; Hoyoung Tang; Hayoung Kim; Dongwook Seo; Hoonki Kim; Woojin Rim; Sanghoon Baek; Sangyeop Baeck; Jonghoon Jung (CICC, 2022)

Standard Cell Design Optimization with Advanced MOL Technology in 3nm GAA Process. - Giyoung Yang; Hakchul Jung; Jinyoung Lim; Jaewoo Seo; Ingyum Kim; Jisu Yu; Hyeoungyu You; Jeongsoon Kong; Garoom Kim; Minjae Jeong; Chanhee Park; Sera An; et al. (VLSI Technology and Circuits, 2022)

A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit. - Taejoong Song; Hoonki Kim; Woojin Rim; Hakchul Jung; Changnam Park; Inhak Lee; Sanghoon Baek; Jonghoon Jung (IEEE J. Solid State Circuits, 2022)

Boundary-Power Overlapped Design for Sub-3nm Standard Cell Placement. - Jaeha Lee; Woonseon Cheon; Yunseok Noh; Huijae Lim; Subin Jin; Shinwoo Kim; Hayoung Kim; Sanghoon Baek (ISVLSI, 2025)