A 690mV 4.4Gbps/pin all-digital LPDDR4 PHY in 10nm FinFET technology. - Kwanyeob Chae; JongRyun Choi; Shinyoung Yi 002; Won Lee; Sanghoon Joo; Hyunhyuck Kim; Hyungkwon Yi; Yoonjee Nam; Jinho Choi; Sanghune Park; Sanghyun Lee (ESSCIRC, 2016)

23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller. - Soo-Min Lee; Jihun Oh; Jinho Choi; Seokkyun Ko; Daero Kim; Kyounghoi Koo; JongRyun Choi; Yoonjee Nam; Sangsoo Park; Hyungkweon Lee; Eunsu Kim; Sukhyun Jung; et al. (ISSCC, 2017)

Digital PHY Design Methodologies for High-Speed and Low-Power Memory Interface. - Kwanyeob Chae; Billy Koo; Jihun Oh; Sanghune Park; Jongshin Shin; Jaehong Park (ISOCC, 2018)

A Low-Power Post-LPDDR4 Interface Using AC Termination at RX and an Active Inductor at TX. - Jeongsik Yoo; Yeonho Lee 002; Yoonjae Choi; Hyunsu Park; Sanghune Park; Chulwoo Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

An 8nm All-Digital 7.3Gb/s/pin LPDDR5 PHY with an Approximate Delay Compensation Scheme. - Kwanyeob Chae; JongRyun Choi; Hyungkwon Lee; Jinho Choi; Shinyoung Yi 002; Yoonjee Nam; Sangyun Hwang; Joohyung Lee; Won Lee; Kihwan Seong; Joohee Shin; Soo-Min Lee; et al. (VLSI Circuits, 2019)

22.5 An 8nm 18Gb/s/pin GDDR6 PHY with TX Bandwidth Extension and RX Training Technique. - Soo-Min Lee; Kihwan Seong; Joohee Shin; Hyoungjoong Kim; Jaehyun Jeong; Shinyoung Yi 002; Juyoung Kim; Eunsu Kim; Sukhyun Jung; Sangyun Hwang; Jihun Oh; Kwanyeob Chae; et al. (ISSCC, 2020)

A 16GHz 33fs rms Integrated Jitter FLL-less Gear Shifting Reference Sampling PLL. - Jusung Lee; Youngwoo Jo; Wonsik Yu; WooSeok Kim; Michael Choi; Sanghune Park; Jongshin Shin (CICC, 2023)

A 4nm 1.15TB/s HBM3 Interface with Resistor-Tuned Offset-Calibration and In-Situ Margin-Detection. - Kwanyeob Chae; Jiyeon Park; Jaegeun Song; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Taekyung Yeo; Kyeongkeun Kang; Sangsoo Park; Eunsu Kim; et al. (ISSCC, 2023)

A 4nm 32Gb/s 8Tb/s/mm Die-to-Die Chiplet Using NRZ Single-Ended Transceiver With Equalization Schemes And Training Techniques. - Kihwan Seong; Donguk Park; Gyeom-Je Bae; Hyunwoo Lee; Youngseob Suh; Wooseuk Oh; Hyemun Lee; Juyoung Kim; Takgun Lee; Geonhoo Mo; Sukhyun Jung; Dongcheol Choi; et al. (ISSCC, 2023)

A 4-nm 1.15 TB/s HBM3 Interface With Resistor-Tuned Offset Calibration and In Situ Margin Detection. - Kwanyeob Chae; Jaegeun Song; Yoonjae Choi; Jiyeon Park; Billy Koo; Jihun Oh; Shinyoung Yi 002; Won Lee; Dongha Kim; Kyeongkeun Kang; Eunsu Kim; Juyoung Kim; et al. (IEEE J. Solid State Circuits, 2024)