A 1.6-Gb/s/pin double data rate SDRAM with wave-pipelined CAS latency control. - Sang-Bo Lee; Seong-Jin Jang 002; Jin-Seok Kwak; Sang-Jun Hwang 001; Young-Hyun Jun; Soo-In Cho; Chil-Gee Lee (IEEE J. Solid State Circuits, 2005)

A New Organic Thin-Film Transistor Based Current-Driving Pixel Circuit for Active-Matrix Organic Light-Emitting Displays. - Aram Shin; Sang Jun Hwang 001; Seung Woo Yu; Man Young Sung (ISQED, 2007)

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion. - Jeong-Don Ihm; Seung-Jun Bae; Kwang-Il Park; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Ho-Kyung Lee; Min-Sang Park; Sam-Young Bang; Mi-Jin Lee; Gil-Shin Moon; et al. (ISSCC, 2007)

A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface. - Sang Joon Hwang 001; Young-Hyun Jun; Man Young Sung (IEICE Electron. Express, 2008)

Design of Organic TFT Pixel Electrode Circuit for Active-Matrix OLED Displays. - Aram Shin; Sang Jun Hwang 001; Seung Woo Yu; Man Young Sung (J. Comput., 2008)

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion. - Seung-Jun Bae; Kwang-Il Park; Jeong-Don Ihm; Ho-Young Song; Woo-Jin Lee; Hyun-Jin Kim; Kyoung-Ho Kim; Yoon-Sik Park; Min-Sang Park; Hong-Kyong Lee; Sam-Young Bang; Gil-Shin Moon; et al. (IEEE J. Solid State Circuits, 2008)

Defect Analysis and Cost-Effective Resilience Architecture for Future DRAM Devices. - Sang-uhn Cha; Seongil O; Hyunsung Shin; Sangjoon Hwang 001; Kwang-Il Park; Seong-Jin Jang 002; Joo-Sun Choi; Gyo-Young Jin; Young Hoon Son; Hyunyoon Cho; Jung Ho Ahn; Nam Sung Kim (HPCA, 2017)

A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface. - Dongku Kang; Minsu Kim 004; Suchang Jeon; Wontaeck Jung; Jooyong Park; Gyo Soo Choo; Dong-Kyo Shim; Anil Kavala; Seungbum Kim; Kyung-Min Kang; Jiyoung Lee; Kuihan Ko; et al. (ISSCC, 2019)

13.1 A 1Tb 4b/cell NAND Flash Memory with tPROG=2ms, tR=110µs and 1.2Gb/s High-Speed IO Rate. - Doo-Hyun Kim; Hyunggon Kim; Sung-Won Yun; Youngsun Song; Jisu Kim; Sung-Min Joe; Kyung-Hwa Kang; Joonsuc Jang; Hyun-Jun Yoon; Kangbin Lee; Minseok Kim; Joonsoo Kwon; et al. (ISSCC, 2020)

A 1.8 Gb/s/pin 16Tb NAND Flash Memory Multi-Chip Package with F-Chip of Toggle 4.0 Specification for High Performance and High Capacity Storage Systems. - Jang-Woo Lee; Dae-Hoon Na; Anil Kavala; Hwasuk Cho; Junha Lee; Manjae Yang; Eunjin Song; Tongsung Kim; Seon-Kyoo Lee; Dong-Su Jang; Byung-Kwan Chun; Youngmin Jo; et al. (VLSI Circuits, 2020)

Industry's First 7.2 Gbps 512GB DDR5 Module. - Sung Joo Park; Jonghoon J. Kim; Kun Joo; Young-Ho Lee; Kyoungsun Kim; Young-Tae Kim; Woo-Jin Na; IkJoon Choi; Hye-Seung Yu; Wonyoung Kim; Ju-Yeon Jung; Jaejun Lee; et al. (HCS, 2021)

A Reflection and Crosstalk Canceling Continuous-Time Linear Equalizer for High-Speed DDR SDRAM. - Seunghwan Hong; Chang-Hyun Bae; Yoo-Chang Sung; Jaewoong Kim; Junsub Yoon; Sangwoo Kim; Jin-Hyeok Baek; Cheongryong Cho; Useung Shin; Sang-Kyeom Kim; Hwan-Chul Jung; Ho-Jun Chang; et al. (VLSI Circuits, 2021)

A 16Gb 9.5Gb/S/pin LPDDR5X SDRAM With Low-Power Schemes Exploiting Dynamic Voltage-Frequency Scaling and Offset-Calibrated Readout Sense Amplifiers in a Fourth Generation 10nm DRAM Process. - Dae-Hyun Kim 003; Byungkyu Song; Hyun-A. Ahn; Woongjoon Ko; Sung-Geun Do; Seokjin Cho; Kihan Kim; Seung-Hoon Oh; Hye-Yoon Joo; Geuntae Park; Jin-Hun Jang; Yong-Hun Kim; et al. (ISSCC, 2022)

A 16Gb 27Gb/s/pin T-coil based GDDR6 DRAM with Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus. - Daewoong Lee; Hye-Jung Kwon; Daehyun Kwon; Jaehyeok Baek; Chulhee Cho; Sanghoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (ISSCC, 2022)

A 16 GB 1024 GB/s HBM3 DRAM with On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Young-Cheon Kwon; Jaehoon Lee 005; Sung-Gi Ahn; Jaewon Park; Kijun Lee; Yu Ho Choi; Han-Won Cho; Jae San Kim; Jungyu Lee 002; Haesuk Lee; Seung Ho Song; et al. (VLSI Technology and Circuits, 2022)

DSAC: Low-Cost Rowhammer Mitigation Using In-DRAM Stochastic and Approximate Counting Algorithm. - Seungki Hong; Dongha Kim; Jaehyung Lee; Reum Oh; Changsik Yoo; Sangjoon Hwang 001; Jooyoung Lee (CoRR, 2023)

A 16-Gb T-Coil-Based GDDR6 DRAM With Merged-MUX TX, Optimized WCK Operation, and Alternative-Data-Bus Achieving 27-Gb/s/Pin in NRZ. - Daewoong Lee; Jaehyeok Baek; Hye-Jung Kwon; Daehyun Kwon; Chulhee Cho; Sang-Hoon Kim; Donggun An; Chulsoon Chang; Unhak Lim; Jiyeon Im; Wonju Sung; Hye-Ran Kim; et al. (IEEE J. Solid State Circuits, 2023)

A 16 GB 1024 GB/s HBM3 DRAM With Source-Synchronized Bus Design and On-Die Error Control Scheme for Enhanced RAS Features. - Yesin Ryu; Sung-Gi Ahn; Jaehoon Lee 005; Jaewon Park; Yong-Ki Kim; Hyochang Kim 002; Yeong Geol Song; Han-Won Cho; Sunghye Cho; Seung Ho Song; Haesuk Lee; Useung Shin; et al. (IEEE J. Solid State Circuits, 2023)

A Single-Ended Offset-Compensating Bit-Line Sense-Amplifier with Ground Precharge and Charge Transfer Pre sensing for Sub-1V DRAM. - Changyoung Lee; Youngseok Park; Hyunchul Yoon; Seryeong Yoon; Donggeon Kim; Bokyeon Won; Junhwa Song; Injae Bae; Jae-Joon Song; Kyuchang Kang; Jaehyuk Kim; Kyungrak Cho; et al. (A-SSCC, 2024)

13.6 A 16Gb 37Gb/s GDDR7 DRAM with PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sanghoon Kim; Daewoong Lee; Seongyeal Yang; Gil-Young Kang; Juseop Park; Kyungho Lee; Hwan-Chul Jung; Gun-hee Cho; et al. (ISSCC, 2024)

13.2 A 32Gb 8.0Gb/s/pin DDR5 SDRAM with a Symmetric-Mosaic Architecture in a 5th-Generation 10nm DRAM Process. - IkJoon Choi; Seunghwan Hong; Kihyun Kim; Jeongsik Hwang; Seunghan Woo; Young-Sang Kim; Cheongryong Cho; Eun-Young Lee; Hun-Jae Lee; Min-Su Jung; Hee-Yun Jung; Ju-Seong Hwang; et al. (ISSCC, 2024)

Single Metal BCAT Breakthrough to Open a New Era of 12 nm DRAM and Beyond. - Kyosuk Chae; Taiuk Rim; Youngwoo Son; Heejae Choi; Jin-Seong Lee; Shinwoo Jeong; Jieun Lee; Dongin Lee; Byunghyun Lee; Dongsoo Woo; Seguen Park; Sangjun Hwang 001 (VLSI Technology and Circuits, 2024)

An Offset-Compensated Charge-Transfer Pre-Sensing Bit-Line Sense-Amplifier for Low-Voltage DRAM. - Kyeongtae Nam; Jaehyuk Kim; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jaejoon Song; Incheol Nam; Young-Hun Seo; et al. (VLSI Technology and Circuits, 2024)

Improvement of IGZO BTI for DRAM Cell application by heat treatment and recovery effect. - Changsik Kim; Jongmoo Lee; Jihee Jun; Chanhee Han; In-Jae Bae; Youngkwan Park; Hana Cho; Hyeontae Kim; Dongsik Park; Heonjun Ha; Jae-Joon Song; Changsik Yoo; et al. (IRPS, 2025)

A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process. - Jin-Hyeok Baek; Jang-Hoo Kim; Yoo-Chang Sung; Jae-Woo Jeong; Jin-Kwan Park; Hyun-Kyu Oh; Bo-Hyeon Lee; Dong-Wan Ko; Tae-Seob Oh; Seung-Gi Hong; Chang-Ki Kwon; Daihyun Lim; et al. (ISSCC, 2025)

30.3 A 24Gb 42.5Gb/s GDDR7 DRAM with Low-Power WCK Distribution, an RC-Optimized Dual-Emphasis TX, and Voltage/Time-Margin-Enhanced Power Reduction. - Sang-Hoon Kim; Jaehyeok Baek; Moon-Chul Choi; Daewoong Lee; Donggun An; Se-Mi Kim; Yeonggeun Song; Minkyo Shim; Sung-Yong Cho; Dongha Lee; Gun-hee Cho; Inwoo Jun; et al. (ISSCC, 2025)

A Fine and Massive Test Methodology for Analyzing Core Characteristics in the Development of Next Generation DRAM. - Min-Kyu Kim; Incheol Nam; Minju Shin; Kyungrak Cho; Gijong Sung; Deasun Kim; Heeil Hong; SangJoon Hwang 001 (ITC, 2025)

A 16-Gb 37-Gb/s GDDR7 DRAM With PAM3-Optimized TRX Equalization and ZQ Calibration. - Sung-Yong Cho; Moon-Chul Choi; Jaehyeok Baek; Donggun An; Sang-Hoon Kim; Daewoong Lee; Seongyeal Yang; Se-Mi Kim; Gil-Young Kang; Juseop Park; Kyung-Ho Lee; Hwan-Chul Jung; et al. (IEEE J. Solid State Circuits, 2025)

An Offset Compensated Charge Transfer Pre-Sensing Bitline Sense Amplifier. - Kyeongtae Nam; Dongil Lee; Kyuchang Kang; Sangyun Kim; Changyoung Lee; Hyunchul Yoon; Donggeon Kim; Bokyeon Won; Jae-Joon Song; Jaehyuk Kim; Incheol Nam; Young-Hun Seo; et al. (IEEE J. Solid State Circuits, 2025)

15.6 A 36GB 3.3TB/S HBM4 DRAM with Per-Channel TSV RDQS Auto Calibration and Fully-Programmable MBIST. - Sunghwan Joo; Jinyeon Kim; Yongsun Lee; Ji-Young Kim; Youngsik Lee; Yong-Min Kim; Chi Sung Oh; Kyu-Ha Shim; Haesuk Lee; Young-Yong Byun; ChangHyun Bae; Joohwan Kim; et al. (ISSCC, 2026)

A 16Gb 12.8Gb/s LPDDR6 SDRAM with 12-DQ/Sub-Channel Wide NRZ Signaling and Enhanced Reliability by Per-Row Activation Counting and Meta-Data Scheme. - Kiheung Kim; Hong-Joo Song; Youngdo Um; Jinhun Jang; Seungjun Lee; Ho-Seok Seol; Hye-Jung Kwon; Ji-Hwan Seol; Hoon Shin; Jaehyung Lee; JongMoon Choi; Sung-Woo Yoon; et al. (ISSCC, 2026)

15.10 A Vertical-Cell-Transistor-Based 4F2 DRAM with Cell-on-Peripheral Architecture Using Wafer-to-Wafer Hybrid Copper Bonding. - Hyunchul Yoon; Youngseok Park; Tae Jin Park; Suk Lae Kim; Seungjae Jung; Daesun Kim; Kyunghwan Kim; Yongjun Kim; KyuChang Kang; Bokyeon Won; Sang-Hoon Jung; Seunghan Woo; et al. (ISSCC, 2026)

S-Tiering: A Unified HW/SW Solution for Memory Tiering Based on the Standard CXL Hotness Monitoring Unit. - Seunghak Lee; Wonjae Lee 001; Hojin Nam; Jehoon Park; Youngshin Park; Heesoo Kim; Junhyeok Im; Jinin So; Raghu Vamsi Krishna Talanki; Praful Ramesh O; Rajeev Verma; Taeksang Song; et al. (IEEE Trans. Computers, 2026)

Pangaea v2: CXL-Based Disaggregated Memory System Architecture for Cloud-Native Orchestration. - Han Deok Lee; Jehoon Park; Younghyun Lee; Junhyeok Im; Jin Jung; Jinin So; Siamak Tavallaei; Taehoon Lee; Woo Taek Shim; Chin-Hua Chang; Jianping Jiang; Sungwook Ryu; et al. (IEEE Trans. Computers, 2026)