A 1.1V 2y-nm 4.35Gb/s/pin 8Gb LPDDR4 mobile device with bandwidth improvement techniques. - Keunsoo Song; Sangkwon Lee; Dongkyun Kim; Youngbo Shim; Sangil Park; Bokrim Ko; Duckhwa Hong; Yongsuk Joo; Wooyoung Lee; Yongdeok Cho; Wooyeol Shin; Jaewoong Yun; et al. (CICC, 2014)

An off-chip input capacitor-less boost converter with fast MPPT for energy harvesting. - Sangkwon Lee; Jinseong Jeong (IEICE Electron. Express, 2014)

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme, and duty-training circuit for mobile applications. - Hae-Kang Jung; Jaemo Yang; Jeonghun Lee; Hyeongjun Ko; Hyuk Lee; Taeksang Song; Jongjoo Shim; Sangkwon Lee; Keunsoo Song; Dongkyun Kim; Hyungsoo Kim; Yunsaing Kim (VLSIC, 2015)

A 1.1 V 2y-nm 4.35 Gb/s/pin 8 Gb LPDDR4 Mobile Device With Bandwidth Improvement Techniques. - Keunsoo Song; Sangkwon Lee; Dongkyun Kim; Youngbo Shim; Sangil Park; Bokrim Ko; Duckhwa Hong; Yongsuk Joo; Wooyoung Lee; Yongdeok Cho; Wooyeol Shin; Jaewoong Yun; et al. (IEEE J. Solid State Circuits, 2015)

A 25-mV input boost converter with 91% MPPT efficiency for energy harvesting application. - Sangkwon Lee; Jinseong Jeong (IEICE Electron. Express, 2018)

A fast maximum power point tracking boost converter with 80 ns sampling and tracking time for energy harvesting application. - Sangkwon Lee; Jinseong Jeong (IEICE Electron. Express, 2019)

22.3 A 128Gb 8-High 512GB/s HBM2E DRAM with a Pseudo Quarter Bank Structure, Power Dispersion and an Instruction-Based At-Speed PMBIST. - Dong-Uk Lee; Ho Sung Cho; Jihwan Kim; Young Jun Ku; Sangmuk Oh; Chul Dae Kim; Hyun Woo Kim; Wooyoung Lee; Tae-Kyun Kim 001; Tae Sik Yun; Min Jeong Kim; SeungGyeon Lim; et al. (ISSCC, 2020)

A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation. - Kyunghoon Kim; Joo-Hyung Chae; Jaehyeok Yang; Jihyo Kang; Gang-Sik Lee; Sang-Yeon Byeon; Youngtaek Kim; Boram Kim; Dong-Hyun Kim; Yeongmuk Cho; Kangmoo Choi; Hyeongyeol Park; et al. (ISSCC, 2021)

A 192-Gb 12-High 896-GB/s HBM3 DRAM with a TSV Auto-Calibration Scheme and Machine-Learning-Based Layout Optimization. - Myeong-Jae Park; Ho Sung Cho; Tae-Sik Yun; Sangjin Byeon; Young Jun Koo; Sang-Sic Yoon; Dong-Uk Lee; Seokwoo Choi; Ji Hwan Park; Jinhyung Lee; Kyungjun Cho; Junil Moon; et al. (ISSCC, 2022)

A 24-Gb/s/Pin 8-Gb GDDR6 With a Half-Rate Daisy-Chain-Based Clocking Architecture and I/O Circuitry for Low-Noise Operation. - Jihyo Kang; Jaehyeok Yang; Kyunghoon Kim; Joo-Hyung Chae; Gang-Sik Lee; Sang-Yeon Byeon; Boram Kim; Dong-Hyun Kim; Youngtaek Kim; Yeongmuk Cho; Junghwan Ji; Sera Jeong; et al. (IEEE J. Solid State Circuits, 2022)

A Clock Distribution Scheme Insensitive to Supply Voltage Drift With Self-Adjustment of Clock Buffer Delay. - Soyeong Shin; Yongjae Lee; Jiheon Park; Jihyo Kang; Kyunghoon Kim; Dae-Han Kwon; Sangkwon Lee; Jieun Jang; Joo-Hwan Cho; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)