A 2.8-to-7.2GT/s DDR5 Registering Clock Driver IC with Parallel-Data Timing and Pin-to-Pin Skew Calibration for a Dual In-Line Memory Module. - Joomyoung Kim; Jaehong Jung; Kwangmin Lim; Barosaim Sung; Jaekwon Kim; Baekmin Lim; Tae-Gun Noh; Jaehoon Lee 005; Hyun-Gi Seok; Youngsea Cho; Gyusik Kim; Takahiro Nomiyama; et al. (A-SSCC, 2024)

10.4 A 2- TRX IR-UWB Transceiver with Shared Antennas Supporting Channels 5 to 12 in Compliance with IEEE 802.15.4/4z Standards. - Hyun-Gi Seok; Jae-Keun Lee; Sinyoung Kim; Wonjun Jung; Honggul Han; Junhyeong Kim; Sumin Kang; Chanho Kim; Wonkang Kim; Jongpil Cho; Seungyong Bae; Yanghoon Lee; et al. (ISSCC, 2025)